Hyuk-ju Ryu
Samsung
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Hyuk-ju Ryu.
symposium on vlsi technology | 2004
Hyuk-ju Ryu; Woo-young Chung; You-Jean Jang; Yong-Jun Lee; Hyung-Seok Jung; Chang-bong Oh; Hee-Sung Kang; Young-Wug Kim
Ultra low power 1.10 /spl mu/m/sup 2/ 6T-SRAM chip with HfO/sub 2/-Al/sub 2/O/sub 3/ gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO/sub 2/-Al/sub 2/O/sub 3/ film was 17/spl Aring/ and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO/sub 2/-Al/sub 2/O/sub 3/ were 335 and 115 /spl mu/A/ /spl mu/m, while Ioff were 0.9 and 2.0pA/ /spl mu/m, respectively. SNM value of 1.10 /spl mu/m/sup 2/ 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.
symposium on vlsi technology | 2003
Chang-bong Oh; Hyuk-ju Ryu; Hee-Sung Kang; Myoung-hwan Oh; Jong-Ho Lee; Nae-In Lee; Hyun-Woo Lee; Cheol-Hee Jun; Young-Wug Kim; Kwang-Pyuk Suh
Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric were successfully demonstrated (bit-cell size=2.14 /spl mu/m/sup 2/). Equivalent oxide thickness (EOT) of 1.56 nm, the thin high-k gate dielectric NMOS and PMOS transistor had 470 and 150 /spl mu/A//spl mu/m at Ioff=0.1 nA//spl mu/m and Vdd=1.2 V, respectively. By deliberate optimizing the conditions of post nitridation and post deposition annealing (PDA) such as O/sub 2/ and N/sub 2/ PDA temperature, 60 and 82% of NMOS and PMOS mobility, respectively, compared to those of oxynitride were achieved without increasing EOT. And also, reliabilities of TDDB and HCI, and flicker noise characteristics of the thin high-k transistors were improved. For the 6T-SRAM with optimized thin high-k gate dielectric, static noise margin (SNM), cell delay, and chip yield were comparable to those of the oxynitride device while dynamic power was more than 2 orders lower (Vdd=1.0/spl sim/1.2 V).
Archive | 2003
Hyuk-ju Ryu; Young-Wug Kim; Chang-bong Oh; Hee-Sung Kang
Archive | 2003
Hyuk-ju Ryu; Jong-Hyon Ahn
Archive | 2007
Kyung-Soo Kim; Young-Wug Kim; Chang-bong Oh; Hee-Sung Kang; Hyuk-ju Ryu
Archive | 2005
Mu-kyeng Jung; Hee-Sung Kang; Hyuk-ju Ryu; Woo-young Chung; Kyung-Soo Kim
Archive | 2002
Hyuk-ju Ryu; Young-Gun Ko
Archive | 2006
Hyuk-ju Ryu; Heon-jong Shin; Hee-Sung Kang; Choong-Ryul Ryou; Mu-kyeng Jung; Kyung-Soo Kim
Archive | 2007
Hyuk-ju Ryu; Hee-Sung Kang; Kyung-Soo Kim
Archive | 2004
You-Seung Jin; Jong-Hyon Ahn; Hyuk-ju Ryu