Jong-Hyuk Kang

Novel method for measurement of transistor gate length using energy-filtered transmission electron microscopy

As the feature size of devices continues to decrease, transmission electron microscopy (TEM) is becoming indispensable for measuring the critical dimension (CD) of structures. Semiconductors consist primarily of silicon-based materials such as silicon, silicon dioxide, and silicon nitride, and the electrons transmitted through a plan-view TEM sample provide diverse information about various overlapped silicon-based materials. This information is exceedingly complex, which makes it difficult to clarify the boundary to be measured. Therefore, we propose a simple measurement method using energy-filtered TEM (EF-TEM). A precise and effective measurement condition was obtained by determining the maximum value of the integrated area ratio of the electron energy loss spectrum at the boundary to be measured. This method employs an adjustable slit allowing only electrons with a certain energy range to pass. EF-TEM imaging showed a sharp transition at the boundary when the energy-filters passband centre was set at 90 eV, with a slit width of 40 eV. This was the optimum condition for the CD measurement of silicon-based materials involving silicon nitride. Electron energy loss spectroscopy (EELS) and EF-TEM images were used to verify this method, which makes it possible to measure the transistor gate length in a dynamic random access memory manufactured using 35 nm process technology. This method can be adapted to measure the CD of other non-silicon-based materials using the EELS area ratio of the boundary materials.

Electrical characterization of electron beam induced damage on sub-10 nm n-channel MOS transistors using nano-probing technique

Electron beam induced damage on sub-10 nm n-channel MOS transistors was evaluated using an atomic force microscopy-based nano-probing technique. After electron beam irradiation, all the device parameters shifted including threshold voltage (V th), saturation current, sub-threshold slope and transistor leakage current. A negative shift in V th occurred at low electron beam acceleration voltage (V acc) because of the increase in oxide trapped holes generated by excited plasmons. At high V acc, however, a positive V th shift was observed because of an increased contribution of interface trap generation caused by the deeper electron penetration depth. In addition, interface trap generation not only degraded the sub-threshold slope due to the additional capacitance from the generated interface traps, but also increased transistor leakage current due to changes in junction characteristics. Our studies show that it is critical to avoid electron beam exposure before electrical characterization on sub-10 nm devices even in the range of less than 1.0 kV of V acc using nano-probe systems.