Jong-ryeol Yoo

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease

Improved post-cycling characteristic of FinFET NAND Flash

In this paper, SONOS type FinFET device has been fabricated and characterized for the NAND flash application. Pre- and post-cycling characteristics are mainly studied both for the FinFET and planar device, with respect to the memory cell performance and device reliability. It has been demonstrated that the performance improvement of the FinFET is maintained after cycling stress, and most importantly, the superior bake retention characteristic of FinFET device is observed after cycling stress compared to the planar device

Electrical Characteristics of Ultrashallow p + ∕ n Junction Formed by BF3 Plasma Doping and Two-Step Annealing Process

We have investigated ultrashallow p + /n junctions formed by BF 3 plasma doping. Conventional one-step annealing processes such as rapid thermal annealing or excimer laser annealing (ELA) are not effective methods for high activation of boron. Furthermore, it is known that fluorine can retard dopant activation. In order to reduce fluorine concentration, we propose additional preannealing at 600°C for 10 min followed by ELA. This process dramatically improved the boron activation ratio, while maintaining the same junction depth. The improvement of dopant activation is attributed to significant out-diffusion of fluorine which in turn enhances activation of boron during ELA.

Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques

This paper describes thermal desorption silicon etching (TDSE)/channel-epi transistor, which has improved the profile and the electrical characteristics of channel-epi transistor. Thermal desorption silicon etching (TDSE) process is introduced before Si channel-epi growth using ultrahigh vacuum system to improve transistor performance at dynamic random access memory (DRAM) device. TDSE process for etching active silicon was carried out using Cl2 gas at 700°C in UHV chamber. Following the TDSE process, in-situ Si channel-epi was grown at the same chamber. We evaluated the electrical characteristics of TDSE/channel-epi transistor, and also measured the reliability of gate oxide. Compared with the conventional channel-epi which shows the degradation of transistor characteristics due to the raised active profile, TDSE process with channel-epi presents superior transistor performance in terms of transistor hump characteristics and inverse narrow width effect (INWE). TDSE induced interface and junction leakages, however, are observed. To solve these problems, H2 added TDSE process or H2 anneal process after TDSE has been developed.

High performance cell technology featuring sub-100nm DRAM with multi-gigabit density

Fully metal embedded cell technologies, including poly-Si/W/sub x/N/W gate, Co salicide with elevated source/drain using UHV-selective epitaxial growth and CVD-W cell pad has been integrated successfully for the first time for 100 nm design rule DRAM devices. Each key technology exhibits excellent performance.