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Featured researches published by Woong-Hee Sohn.


Japanese Journal of Applied Physics | 2005

Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

Hyun-Su Kim; Jong-Ho Yun; Kwang-jin Moon; Woong-Hee Sohn; Sug-Woo Jung; Eun-ji Jung; Se-Hoon Kim; Nam-Jin Bae; Gil-heyun Choi; Sung-Tae Kim; U-In Chung; Joo-Tae Moon; Byung-Il Ryu

The improved contact resistance was obtained by the new barrier metal scheme such as CVD-Co/Ti/TiN process in the level of about half of that from CVD-Ti/TiN process. And the mechanism of contact silicidation of CVD-Co/Ti/TiN was investigated. Because Co silicide may prohibit the Si diffusion into Ti silicide and Si recess during TiCl4-based CVD-Ti process, and the inertness of Co silicide to the dopants, the improved contact resistance with uniform silicide morphology was obtained. Therefore, CVD-Co/Ti/TiN contact silicide process can be regarded as the next generation contact silicidation process.


international electron devices meeting | 2003

CVD-cobalt for the next generation of source/drain salicidation and contact silicidation in novel MOS device structures with complex shape

Sang-Bom Kang; Hyun-Su Kim; Kwang-jin Moon; Woong-Hee Sohn; Gil Heyun Choi; S.H. Kim; N.J. Bae; U-In Chung; June Moon

A novel CVD-cobalt process which enables a uniform salicidation even in novel MOS device structures with complex shape is developed for the first time. With CVD-cobalt salicidation, identical values of low sheet resistance can be realized on actives and gates regardless of the surrounding geometry, due to its excellent conformality. In addition, a low contact resistance can be obtained in small metal/active contacts even with high post thermal budget when CVD-Co is applied as an ohmic layer due to its conformality and inertness with the dopants. CVD-cobalt is a needed and suitable solution for the salicidation and silicidation of not only the continuously scaling conventional CMOS, but also the emerging next generation of devices with complex shapes and structures such as vertical and 3D FET.


The Japan Society of Applied Physics | 2004

Investigation of CVD-Co Silicidation for the Improvement of Contact Resistance

Hyun-Su Kim; Jong-Ho Yun; Kwang-jin Moon; Woong-Hee Sohn; Seong-hwee Cheong; Sug-Woo Jung; Gil-heyun Choi; Se-Hoon Kim; Nam-Jin Bae; Sung-Tae Kim; U-In Chung; Joo-Tae Moon

In present, TiCl4-based CVD-Ti/TiN process is widely used to make a TiSi2 ohmic layer in about sub-100nm contacts. But TiCl4 based CVD-Ti/TiN process has some problems such as reactivity of TiSi2 with dopant and rapidly increased contact resistance at small contact CDs. These problems of TiSi2 have limited the implementation and extension of the CVD-Ti./TiN barrier metal process. A novel barrier metal process has been needed for achieving low BL/n+ and BL/p+ contact resistances in the next generation devices with sub-100nm. One of the solutions for these problems is the change of ohmic material from TiSi2 to CoSi2 which has inert characteristics with the dopants for contact ohmic layer. Therefore, CVD-Co process can be a adequate alternative to CVD-Ti process in the development of next generation MOS devices. Recently, Kang et al. have reported that the usefulness of CVD-Co process using CCTBA precursor which has a good step coverage, and which can be also extended to the silicide in 110nm contacts for achieving low contact resistances. In this paper, the results of sub-100nm DC contact resistances with CVD-Co silicide are reported. we studied the reason of the degree of increase of Rc with decreasing contact size was lower with CVD-Co/Ti/TiN at small contacts compared to CVD-Ti/TiN. The mechanism responsible for Cobalt silicidation from CCTBA based CVD-Co in small DC was suggested by analysis of phase transformation and morphology of Co and Ti silicide.


Archive | 2007

Nonvolatile memory devices and methods of fabricating the same

Sanghun Jeon; Chang-seok Kang; Jung-Dal Choi; Jintaek Park; Woong-Hee Sohn; Won-Seok Jung


Archive | 2005

Method of forming a gate of a semiconductor device

Sun-pil Youn; Chang-won Lee; Woong-Hee Sohn; Gil-heyun Choi; Jong-ryeol Yoo; Jang-Hee Lee; Jae-hwa Park; Dong-Chan Lim; Byung-Hak Lee; Hee-sook Park


Archive | 2004

Methods of forming silicide films with metal films in semiconductor devices and contacts including the same

Hyun-Su Kim; Gil-heyun Choi; Jong-Ho Yun; Sug-Woo Jung; Eun-ji Jung; Sang-Bom Kang; Woong-Hee Sohn


Archive | 2010

METHOD OF FORMING BURIED GATE ELECTRODE

Eun-ji Jung; Hyunsoo Kim; Byung-hee Kim; Dae-Yong Kim; Woong-Hee Sohn; Kwang-jin Moon; Jang-Hee Lee; Min-Sang Song; Eun-Ok Lee


Archive | 2005

Methods of forming gate structures for semiconductor devices and related structures

Woong-Hee Sohn; Chang-won Lee; Sun-pil Youn; Gil-heyun Choi; Byung-Hak Lee; Jong-ryeol Yoo; Hee-sook Park


Archive | 2004

Methods for forming cobalt layers including introducing vaporized cobalt precursors and methods for manufacturing semiconductor devices using the same

Hyun-Su Kim; Gil-heyun Choi; Sang-Bom Kang; Woong-Hee Sohn; Jong-Ho Yun; Kwang-jin Moon


Archive | 2005

Recessed gate electrodes having covered layer interfaces and methods of forming the same

Byung-Hak Lee; Chang-won Lee; Hee-sook Park; Woong-Hee Sohn; Sun-pil Youn; Jong-ryeol Yoo

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