Gil-heyun Choi

Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

The improved contact resistance was obtained by the new barrier metal scheme such as CVD-Co/Ti/TiN process in the level of about half of that from CVD-Ti/TiN process. And the mechanism of contact silicidation of CVD-Co/Ti/TiN was investigated. Because Co silicide may prohibit the Si diffusion into Ti silicide and Si recess during TiCl4-based CVD-Ti process, and the inertness of Co silicide to the dopants, the improved contact resistance with uniform silicide morphology was obtained. Therefore, CVD-Co/Ti/TiN contact silicide process can be regarded as the next generation contact silicidation process.

Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.

An effective procedure for sensor variable selection and utilization in plasma etching for semiconductor manufacturing

Abstract Plasma etching processes have a potentially large number of sensor variables to be utilized, and the number of the sensor variables is growing due to advances in real-time sensors. In addition, the sensor variables from plasma sensors require additional knowledge about plasmas, which becomes a big burden for engineers to utilize them in this filed. Thus an effective procedure for sensor variable selection with minimum plasma knowledge is needed to develop in plasma etching. The integrated squared response (ISR) based sensor variable selection method which facilitates collecting and analyzing sensor data at one time with regard to manipulated variables (MVs) is suggested in this paper. The reference sensor library as well as sensor ranking tables constructed on the basis of ISR can give insight into plasma sensors. The ISR based sensor variable selection method is incorporated with relative gain array (RGA) or non-square relative gain array (NRGA) for effective variable selection in building a virtual metrology (VM) system to predict critical dimension (CD) in plasma etching. The application of the technique introduced in this paper is shown to be effective in the CD prediction in plasma etching for a dynamic random access memory (DRAM) manufacturing. The procedure for sensor variable selection introduced in this paper can be a starting point for various sensor-related applications in semiconductor manufacturing.

Properties of isolation liner and electrical characteristics of high aspect ratio TSV in 3D stacking technology

As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of higher bandwidth, smaller form factor and lower power consumption. Such increase in performance using TSV aided 3D chip stacking technology applies not only to homogenous chip stacking but to heterogeneous chip stacking (e.g. memory device on logic) as well, making it ideal for such applications in high performance mobile devices.

Implementation of a robust virtual metrology for plasma etching through effective variable selection and recursive update technology

Virtual metrology (VM) is attracting much interest from semiconductor manufacturers because of its potential advantages for quality control. Plasma etching equipment with state-of-the-art plasma sensors are attractive for implementing VM. However, the plasma sensors requiring physical understanding make it difficult to select input parameters for VM. In addition, those sensors with high sensitivity frequently cause several issues in terms of VM performance. This paper will address plasma sensor issues in implementing a robust VM, where self-excited electron resonance spectroscopy, optical emission spectroscopy, and VI-probe are utilized for critical dimension prediction in a plasma etching process. An optimum sensor selection technique which can give insight into effectiveness of plasma sensors is introduced. In this technique, a numerical criterion, integrated squared response, is proposed for effective selection of important sensors for particular manipulated variables. Sensor data shift across equipmen...

Formation of highly reliable Cu/low-k interconnects by using CVD Co barrier in dual damascene structures

CVD Co film was investigated as an alternative barrier layer to the conventional PVD TaN\Ta in V1\M2 structure for 32nm node. We improved via filling performance and upstream (V1ƒM2) electromigration (EM) lifetime by more than three times. Excellent step coverage of CVD barrier makes it possible to reduce the thickness of the barrier metal by 30% and to increase the volume of Cu in metal lines. RC delay also reduced with decrease in resistance. Since adhesion at the interface between the barrier-Co and Cu also is strong, migration of Cu atoms is dramatically slowed down. EM in the via is finally deterred due to absence of pre-existing voids, consequently lifetime increases. This CVD Co process is expected to be beneficial for the next technology generation beyond 20nm node.

Effect of pre-existing void in sub-30nm Cu interconnect reliability

Pre-existing void effect during electromigration in a sub-30nm wide Cu interconnect was observed. Two types of void are intentionally produced in a single damascene interconnect: 1) A void between Cu and capping dielectric layer (center void) is mainly produced from an excessive overhang by depositing a thick seed layer. 2) A void between Cu and barrier metal (side void) is produced from depositing a thin, discontinuous seed layer. Bi-modality was observed in center voided samples. 44% of lines with center voids show stiff resistance rises at high current density and most of them failed shortly after the resistance rise. No stiff resistance rise was observed at lower current density up to 3000 A.U. In side voided samples, no early failures was observed and the failure show no bimodal trend. Change in local current density around the void is expected to be the major factor for the electromigration performance difference between lines with center and side voids. We were able to show that shape and location of the pre-existing void have a significant effect on the reliability of Cu interconnect, and also the void behavior is highly sensitive to current density.

Multiple input multiple output controller design to match chamber performance in plasma etching for semiconductor manufacturing

In semiconductor manufacturing, multiple chambers utilized for the same process step often experience performance variation. This chamber to chamber performance variation has affected the yield of wafers, but there are no standard procedures to reduce them in semiconductor manufacturing. This paper introduces chamber matching in plasma etching as one of the core issues in semiconductor manufacturing and suggests a step-by-step procedure to address chamber matching issues. A brief review of two approaches, fault detection and classification and equipment control, is given and a step-by-step procedure of the equipment control approach is introduced. To design a multiple input-multiple output controller, a decomposed etch rate map makes it possible to analyze etch rate performance between chambers and to define controlled variables. Optimum variable selection techniques, such as singular value analysis and relative gain array methods, and dynamic optimization with constraints are suggested in this paper. In ...

Successful recovery of moisture-induced TDDB degradation for Cu/ULK(k=2.5) BEOL interconnect

Cu/ULK(k=2.5) dual Damascene back end of line(BEOL) dielectric degradation was studied with respect to post Cu CMP delay prior to dielectric diffusion barrier deposition. The threshold of the delay time was observed beyond which line-to-line leakage current increased rapidly while the dielectric breakdown voltage decreased. This air exposure-dependent degradation was attributed to moisture absorption by damaged ULK during integration, and caused premature TDDB (time-dependent dielectric breakdown) failure. It was found that combination of moisture removal by damage-free UV and mild plasma treatment was able to restore dielectric breakdown voltage as well as TDDB time to failure even well past the threshold of delay time.

Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect

Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface between barrier metal of tungsten via and copper. Time to failure is highly dependent on types of barrier metals applied. Critical stresses for void nucleation at the interface for 3 types of barrier metals are obtained using a simulation tool, and the average stress ranges from 61MPa to 246MPa. Second type of failure, which occurs less frequently than the first type, is by void growth and spanning through width and thickness of the line. Failures by void growth occur at a specific time range and failures are independent of barrier metal variation, which suggests that the failure is initiated by a pre-existing void or a defect. Thus, in order to effectively enhance the EM resistance in this hybrid interconnect structure, one should not only optimize the barrier metal, but also minimize pre-existing voids or defects in the line.