Jonghyun Cho
Missouri University of Science and Technology
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Featured researches published by Jonghyun Cho.
IEEE Transactions on Components, Packaging and Manufacturing Technology | 2011
Joohee Kim; Jun So Pak; Jonghyun Cho; Eakhwan Song; Jeonghyeon Cho; Heegon Kim; Taigon Song; Junho Lee; Hyungdong Lee; Kunwoo Park; Seung-Taek Yang; Min-Suk Suh; Kwang-Yoo Byun; Joungho Kim
We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.
IEEE Transactions on Components, Packaging and Manufacturing Technology | 2011
Jonghyun Cho; Eakhwan Song; Kihyun Yoon; Jun So Pak; Joohee Kim; Woojin Lee; Taigon Song; Kiyeong Kim; Junho Lee; Hyungdong Lee; Kunwoo Park; Seung-Taek Yang; Min-Suk Suh; Kwang-Yoo Byun; Joungho Kim
In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.
IEEE Transactions on Components, Packaging and Manufacturing Technology | 2011
Jun So Pak; Joohee Kim; Jonghyun Cho; Kiyeong Kim; Taigon Song; Seungyoung Ahn; Junho Lee; Hyungdong Lee; Kunwoo Park; Joungho Kim
The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz.
design automation conference | 2011
Chang Liu; Taigon Song; Jonghyun Cho; Joohee Kim; Joungho Kim; Sung Kyu Lim
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller com- pared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show that both approaches are effective in reducing the TSV-caused-coupling and improving timing.
electrical performance of electronic packaging | 2009
Jonghyun Cho; Jongjoo Shim; Eakhwan Song; Jun So Pak; Junho Lee; Hyungdong Lee; Kunwoo Park; Joungho Kim
In this paper, we propose a coupling model between through silicon via (TSV) and substrate based on a 3-Dimensional transmission line matrix (3D-TLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV. The proposed model is verified by S-parameter simulations using a 3D field solver and analyzed with various structural parameters: TSV diameter, distance between TSV and noise source, and silicon substrate height. Based on the model, timing jitter degradation on phase locked loop (PLL) caused by substrate noise coupling is investigated. A shielding technique using a guard ring structure is applied to suppress the coupling noise.
electronic components and technology conference | 2010
Jun So Pak; Jonghyun Cho; Joohee Kim; Junho Lee; Hyungdong Lee; Kunwoo Park; Joungho Kim
The effects of slow wave and dielectric quasi-TEM modes due to MIS (Metal-Insulator-Semiconductor) structure TSV (Through-Silicon-Via) are analyzed by using the proposed MIS TSV model and the measured results. Since MIS TSV has larger surface, longer length, and smaller insulator thickness than those of conventional on-chip metal lines, the stronger effects of slow wave and dielectric quasi-TEM modes of MIS structure on electrical performance appear. After obtaining the MIS structure TSV model with the dimension variables based on the measurement and 3D full wave simulation, two slow wave and dielectric quasi-TEM modes effects on MIS TSV electrical characteristics are analyzed in the aspects of signal propagation and power delivery.
IEEE Transactions on Components, Packaging and Manufacturing Technology | 2012
Heegon Kim; Jonghyun Cho; Myunghoi Kim; Kiyeong Kim; Junho Lee; Hyungdong Lee; Kunwoo Park; Kwang-Seong Choi; Hyun-Cheol Bae; Joungho Kim; Jiseong Kim
Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D interconnections to realize considerable high-bandwidth throughput in vertically stacked and laterally distributed integrated circuits. However, although the TSV and a silicon interposer in a high-speed TSV channel lead to a significant decrease of the interconnect length, the received digital signal after transmission through a TSV channel is still degraded at a high data-rate due to the nonidealities of the channel. Therefore, an analysis of the signal integrity in a high-speed TSV channel is necessary. In this paper, a single-ended high-speed TSV channel is measured and analyzed in the frequency-domain and the time-domain. To measure the high-speed TSV channel, two types of test vehicles are fabricated, consisting of TSVs and interposers. With these test vehicles, the channel losses are measured in the frequency-domain up to 20 GHz, and eye-diagrams are measured in the time-domain at 1 Gb/s and 10 Gb/s. Based on these measurements, the channel loss, characteristic impedance, and reflection of the high-speed TSV channel are analyzed and compared to those of the channel in multichip module (MCM) package. Because of the losses from the silicon-substrate and the thin oxide-layer used in the TSVs, the overall loss of the high-speed TSV channel is higher than that of the MCM channel. In addition, the characteristic impedance of the high-speed TSV channel is frequency-dependent, whereas that of the MCM channel is frequency-independent. Moreover, in contrast to the MCM channel, the reflection is negligible in the high-speed TSV channel because the channel is too short and the losses are too high to be affected by the reflection. Finally, the design guidance of a high-speed TSV channel for wide bandwidth is determined based on the analysis of the measurements.
IEEE Transactions on Components, Packaging and Manufacturing Technology | 2014
Joohee Kim; Jonghyun Cho; Joungho Kim; Jong-Min Yook; Jun Chul Kim; Junho Lee; Kunwoo Park; Jun So Pak
An analytic scalable model of a differential signal through-silicon via (TSV) is proposed. This TSV is a ground-signal-signal-ground (GSSG)-type differential signal TSV. Each proposed analytical equation in the model is a function of the structural and material design parameters of the TSV and the bump, which is scalable. The proposed model is successfully validated with measurements up to 20 GHz for the fabricated test vehicles. Additionally, the scalability of the proposed model is verified with simulations by using Ansoft HFSS to vary the design parameters, such as the TSV diameter, pitch between TSVs, and TSV oxide thickness. On the basis of the proposed scalable model, the electrical behaviors of the GSSG-type differential signal TSV are analyzed with respect to the design variations in the frequency domain. Additionally, the electrical performances of a GSSG-type differential signal TSV are evaluated and compared to that of a ground-signal-ground-type single-ended signal TSV, such as insertion loss, characteristic impedance, voltage/timing margin, and noise immunity.
international symposium on quality electronic design | 2011
Taigon Song; Chang Liu; Dae Hyun Kim; Sung Kyu Lim; Jonghyun Cho; Joohee Kim; Jun So Pak; Seungyoung Ahn; Joungho Kim; Kihyun Yoon
It is widely-known that coupling exists between adjacent through-silicon vias (TSVs) in 3D ICs. Since this TSV-to-TSV coupling is not negligible, it is highly likely that TSV-to-TSV coupling affects crosstalk significantly. Although a few works have already analyzed coupling in 3D ICs, they used S-parameter-based methods under the assumption that all ports in their simulation structures are under 50-Ω termination condition. However, this 50-Ω termination condition does not occur at ports (pins) of gates inside a 3D IC. In this paper, therefore, we analyze TSV-to-TSV coupling in 3D ICs based on a lumped circuit model with a realistic high-impedance termination condition. We also analyze how channel affect TSV-to-TSV coupling differently in different frequency ranges. Based on our results, we propose a technique to reduce TSV-to-TSV coupling in 3D ICs.
international symposium on electromagnetic compatibility | 2012
Hongseok Kim; Jonghyun Cho; Seungyoung Ahn; Jonghoon Kim; Joungho Kim
This paper describes a method to suppress the leakage magnetic field from a wireless power transfer (WPT) system through the use of a ferrimagnetic material and metallic shielding. To demonstrate the advantages of the coil structure with the ferrimagnetic material and metallic shielding, magnetic field distributions and the electrical performance of three different coil structures are investigated via 3D electromagnetic (EM) field solver and SPICE simulation. Results show that the suggested method considerably reduces the leakage magnetic field in the vicinity of the WPT system without significant loss of electrical performance. The simulation results of the suggested coil structure are experimentally verified with a 100 W-class WPT system for an LED TV.