Kiyeong Kim

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz.

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structures impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

Measurement and Analysis of a High-Speed TSV Channel

Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D interconnections to realize considerable high-bandwidth throughput in vertically stacked and laterally distributed integrated circuits. However, although the TSV and a silicon interposer in a high-speed TSV channel lead to a significant decrease of the interconnect length, the received digital signal after transmission through a TSV channel is still degraded at a high data-rate due to the nonidealities of the channel. Therefore, an analysis of the signal integrity in a high-speed TSV channel is necessary. In this paper, a single-ended high-speed TSV channel is measured and analyzed in the frequency-domain and the time-domain. To measure the high-speed TSV channel, two types of test vehicles are fabricated, consisting of TSVs and interposers. With these test vehicles, the channel losses are measured in the frequency-domain up to 20 GHz, and eye-diagrams are measured in the time-domain at 1 Gb/s and 10 Gb/s. Based on these measurements, the channel loss, characteristic impedance, and reflection of the high-speed TSV channel are analyzed and compared to those of the channel in multichip module (MCM) package. Because of the losses from the silicon-substrate and the thin oxide-layer used in the TSVs, the overall loss of the high-speed TSV channel is higher than that of the MCM channel. In addition, the characteristic impedance of the high-speed TSV channel is frequency-dependent, whereas that of the MCM channel is frequency-independent. Moreover, in contrast to the MCM channel, the reflection is negligible in the high-speed TSV channel because the channel is too short and the losses are too high to be affected by the reflection. Finally, the design guidance of a high-speed TSV channel for wide bandwidth is determined based on the analysis of the measurements.

Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.

Interposer Power Distribution Network (PDN) Modeling Using a Segmentation Method for 3-D ICs With TSVs

In this paper, we propose models for large-sized silicon interposer power distribution networks (PDNs) and through silicon via (TSV)-based stacked grid-type PDNs using a segmentation method. We model the PDNs as distributed scalable resistance (R), inductance (L), conductance (G), and capacitance (C)-lumped models for an accurate estimation of the PDN impedance, including PDN inductance and wave phenomena such as the mode resonance at the high end of the frequency range. For this estimation, it is necessary to accurately model all transmission line (TL) sections that form the PDNs using a conformal mapping method and a phenomenological loss equivalence method (PEM). After modeling the individual TL sections, all the TL sections are connected based on a segmentation method, which is a matrix calculation method. The segmentation method accelerates the calculation speed for the PDN impedance estimation. The proposed models are successfully validated by simulations and measurements in the frequency range 0.1-20 GHz. Using the proposed models, we estimate and analyze the impedance curves of the interposer PDN and TSV-based stacked grid-type PDN with respect to the variations in the horizontal area of the interposer PDN and the number of power/ground TSVs in TSV-based stacked grid-type PDNs, respectively.

Analysis of power distribution network in TSV-based 3D-IC

To reduce simultaneous switching noise (SSN) in a PDN design of TSV-based GPU system, the impedance properties of the hierarchical PDN in the TSV-based GPU system were estimated and analyzed. The system consisted of triple-stacked TSV-based DRAMs on top of the GPU connected by TSVs, a silicon interposer, and a backside re-distribution layer (BS-RDL). A segmentation-based impedance-estimation method was used for the estimation of the total PDN impedance combining models of the on-chip PDN, the power/ground (P/G) TSV, and the coplanar P/G line in the BS-RDL. The impedance properties of the PDN were also analyzed with respect to variations in the number of P/G TSVs and P/G lines in the BS-RDL and variation of the capacitance of the on-chip decoupling capacitor embedded in the on-chip PDN.

Modeling of an On-Chip Power/Ground Meshed Plane Using Frequency Dependent Parameters

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver.

Modeling Electromagnetic Radiation at High-Density Pcb/connector Interfaces

Electromagnetic radiation for a commercial printed circuit board (PCB) connector is investigated in this paper. The simulation models of the connector are shown to be validated by comparing measured and simulated S-parameters. Analytical formulas are provided to calculate the total loss and the radiated power from a PCB/connector structure when material losses are known. The total power loss for the considered geometry is shown to be dominated by material loss rather than radiated power loss. Termination schemes and additional geometry details in the connector model are also studied for their effects on the radiated power.

Effects of on-chip decoupling capacitors and silicon substrate on power distribution networks in TSV-based 3D-ICs

To analyze the effects of the on-chip decoupling capacitors (on-chip decaps) and silicon substrate on three-dimensional (3D) stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3D-ICs, we propose a model for 3D stacked on-chip PDNs that includes the effects of the on-chip decaps and silicon substrate. The model is the RLGC-lumped model based on the segmentation method and scalable equations derived from physical configurations. The model is successfully validated by the 3D EM simulation using CST MWS up to 20 GHz. Using the proposed model, we analyze the effects of the on-chip decaps and silicon substrate on the impedance of 3D stacked on-chip PDNs with respect to variations in the capacitance and position of on-chip decaps, the conductivity of the silicon substrate, and the height between the on-chip PDN and silicon substrate.