Jongseok Bae

CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals

A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the APT mode, the linear amplifier is switched off and the switching amplifier operates as a normal buck converter to supply DC voltage to the power amplifier according to the average output power. The optimum switch sizes of the switching amplifier were analyzed and applied for each operation mode for higher efficiency. An integrated circuit with a power amplifier and the dual-mode supply modulator was designed and fabricated using a 0.18-μm CMOS process for LTE applications at a frequency of 0.78 GHz. For the 16-QAM uplink LTE signal, the measured efficiency with an ET mode is as high as 45.4%, which is 7.0% higher than that from the stand-alone power amplifier at an average output power of 24 dBm. An efficiency of 14.1% was achieved with an APT mode at an average output power of 9 dBm. This is 3.2% higher than that with the ET mode.

Balanced\/Unbalanced Wideband: A Wideband, Bifilar Transmission-Line Balun

This article presents the design details of a wideband, bifilar transmission-line balun submitted for the student design competition for wideband baluns held during the 2015 IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposium (IMS 2015) in Phoenix, Arizona, and sponsored by the MTT-17 Technical Committee on HF-VHF-UHF Technology.

2.6 GHz GaN-HEMT Doherty power amplifier integrated circuit with 55.5% efficiency based on a compact load network

This paper presents a GaN-HEMT DPA IC based on a compact load network for LTE small cells. The gate widths of the transistors for the carrier and peaking amplifiers are optimized to have the same load impedance of 100 Ω. A shunt inductor is added to compensate for the output capacitor of each transistor with parallel resonance. A x-type high-pass impedance transformer based on lumped components is used to modulate the load impedance. Parallel inductors from the resonant circuit and the impedance transformer are merged for further simplification. As a result, only two inductors remain in the load network. For verification, a 2.6 GHz DPA IC with an on-chip load network and input matching networks was designed and fabricated using a 0.4 μm GaN-HEMT process. The DPA IC exhibited a peak output power of 43.9 dBm. For an LTE signal with a signal bandwidth of 10 MHz and a PAPR of 6.5 dB, a high drain efficiency of 55.5% with an ACLR of −30 dBc was obtained at an average output power of 37.4 dBm.

Design of two-stage fully-integrated CMOS power amplifier for K-band applications

This paper presents a K-band power amplifier integrated circuit using Samsung 65 nm CMOS process. The power amplifier adopts two-stage configuration for high power gain. The input, output, and inter-stage transformers are integrated. By neutralizing gate-drain capacitance using cross-coupled capacitors, the power gain and stability were improved. Its chip size is 0.78 × 0.62 mm2. The implemented two-stage power amplifier showed a power gain of 19.6 dB, a saturated output power of 13.5 dBm, and an efficiency of 7.19 % with a supply voltage of 1.1 V at the frequency band of 24 GHz.

CMOS dynamic supply switching power amplifier for LTE applications

This paper presents a CMOS power amplifier (PA) based on a dynamic supply switching technique for long-term evolution (LTE) applications. The PA integrated circuit includes a supply modulator which consists of two DC-DC converters and a switching circuit for dynamic supply switching (DSS) operation. The supply modulator dynamically supplies either low-or high DC voltage to the drain of the PA. To improve the efficiency for low average output power levels, the low and high DC voltages are adjusted at the outputs of the DC-DC converters according to the average output power. For the 16-QAM LTE signal at a frequency of 1.75 GHz, the DSS PA exhibited a high power-added efficiency (PAE) of 35.8% and an adjacent channel leakage power ratio (ACLR) of -34 dBc at an average output power of 21.8 dBm. This PAE is 3.4% points higher than that of the standalone PA. With adjusted DC voltages, a PAE of 29.42% was achieved at an average output power of 17 dBm while maintaining an ACLR of -34 dBc. This is 13.38% points higher than that of the standalone PA at the same output power.

High-Efficiency GaN-HEMT Doherty Power Amplifier with Compact Harmonic Control Networks

본 논문에서는 long term evolution(LTE) 통신을 위한 2.6 GHz 대역에서 동작하는 고효율 Doherty 전력증폭기를 설계하였다. 2차 및 3차 고조파 임피던스를 조정하기 위한 간단한 구조의 정합 네트워크를 통해 전력증폭기의 고효율 동작을 달성하였다. Doherty 전력증폭기는 다양한 측면에서 장점을 갖는 GaN-HEMT 소자를 이용하여 제작되었으며, 10 MHz의 대역폭 및 6.5 dB 첨두 전력 대 평균 전력비(PAPR)의 특성을 갖는 LTE downlink 신호를 이용하여 측정되었다. 평균 전력 33.4 dBm에서 13.1 dB의 전력 이득, 57.6 %의 전력부가효율(PAE) 및 ?25.7 dBc의 인접채널누설비(ACLR) 특성을 갖는다.This paper presents a Doherty power amplifier(DPA) operating in the 2.6 GHz band for long term evolution(LTE) systems. In order to achieve high efficiency, second and third harmonic impedances are controlled using a compact output matching network. The DPA was implemented using a gallium nitride high electron mobility transistor(GaN-HEMT) that has many advantages, such as high power density and high efficiency. The implemented DPA was measured using an LTE downlink signal with a 10 MHz bandwidth and 6.5 dB PAPR. The implemented DPA exhibited a gain of 13.1 dB, a power-added efficiency(PAE) of 57.6 %, and an ACLR of —25.7 dBc at an average output power of 33.4 dBm.