Wonseob Lim

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

Optimized Current of the Peaking Amplifier for Two-Stage Doherty Power Amplifier

This paper presents a method of improving efficiency for the two-stage Doherty power amplifier (DPA) using the optimized current of the peaking amplifier. The DPA has a two-stage structure for both the carrier and peaking amplifiers. The first stage of the peaking amplifier has an adjusted bias condition for a near Class-B operation, while the first stage of the carrier amplifier has a higher Class-AB operation. The gain expansion of the first stage due to its lower gate bias helps the second stage of the peaking amplifier to be biased for light Class-C operation and to have steeper turn-ON characteristics, which leads higher peak output power and higher back-off efficiency. The two-stage DPA was designed for the 2.655-GHz band. Using a downlink long-term evolution signal with a signal bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, the overall power gain of 25 dB and a peak output power of 54.2 dBm are experimentally obtained. Using an optimized shape of the peaking amplifier’s current, a drain efficiency (DE) of 53% and an adjacent channel leakage power ratio of −30 dBc were obtained at an average output power of 47.8 dBm. A DE of 56.8% and an adjacent channel leakage power ratio of −25 dBc were also obtained at an average output power of 49.5 dBm.

Doherty Power Amplifier Based on the Fundamental Current Ratio for Asymmetric cells

This paper presents a Doherty power amplifier (DPA) based on asymmetric cells using an even input power drive and an appropriate peak fundamental current ratio (FCR) between the peaking amplifier and the carrier amplifier. Using an appropriate output combiner and an even input power drive for the DPA, not only better load modulation but also enhanced power gain can be achieved. After providing an analysis for the fundamental currents, a design guide for the proposed DPA using the peak FCR is presented. For verification, conventional and proposed DPAs were designed using GaN-HEMTs for the 2.14-GHz band. Using a downlink long-term evolution signal having a peak-to-average power ratio of 6.5 dB, comparably better performances were achieved than the conventional DPAs, such as a high power-added efficiency of 55.7% and a power gain of as high as 16.6 dB, at an average output power level of 36.9 dBm.

Dual Bias Modulator for Envelope Tracking and Average Power Tracking Modes for CMOS Power Amplifier

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a 0.18-㎜ CMOS process for the 1.75 ㎓ band. For the 16-QAM LTE signal with a peakto-average power ratio of 7.3 ㏈ and a bandwidth of 5 ㎒, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 ㏈, and an adjacent channel leakage power ratio of -30 ㏈c at an average output power of 22 ㏈m, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 ㏈m.

2.6 GHz GaN-HEMT Doherty power amplifier integrated circuit with 55.5% efficiency based on a compact load network

This paper presents a GaN-HEMT DPA IC based on a compact load network for LTE small cells. The gate widths of the transistors for the carrier and peaking amplifiers are optimized to have the same load impedance of 100 Ω. A shunt inductor is added to compensate for the output capacitor of each transistor with parallel resonance. A x-type high-pass impedance transformer based on lumped components is used to modulate the load impedance. Parallel inductors from the resonant circuit and the impedance transformer are merged for further simplification. As a result, only two inductors remain in the load network. For verification, a 2.6 GHz DPA IC with an on-chip load network and input matching networks was designed and fabricated using a 0.4 μm GaN-HEMT process. The DPA IC exhibited a peak output power of 43.9 dBm. For an LTE signal with a signal bandwidth of 10 MHz and a PAPR of 6.5 dB, a high drain efficiency of 55.5% with an ACLR of −30 dBc was obtained at an average output power of 37.4 dBm.

Design of two-stage fully-integrated CMOS power amplifier for K-band applications

This paper presents a K-band power amplifier integrated circuit using Samsung 65 nm CMOS process. The power amplifier adopts two-stage configuration for high power gain. The input, output, and inter-stage transformers are integrated. By neutralizing gate-drain capacitance using cross-coupled capacitors, the power gain and stability were improved. Its chip size is 0.78 × 0.62 mm2. The implemented two-stage power amplifier showed a power gain of 19.6 dB, a saturated output power of 13.5 dBm, and an efficiency of 7.19 % with a supply voltage of 1.1 V at the frequency band of 24 GHz.

2.6 GHz GaN-HEMT Power Amplifier MMIC for LTE Small-Cell Applications

This paper presents a two-stage power amplifier MMIC using a 0.4 μm GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of 2.0×1.9 mm² and was mounted on a 4×4 QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

Low-Power and High-Efficiency Class-D Audio Amplifier Using Composite Interpolation Filter for Digital Modulators

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital deltasigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of 16 6 and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.

Design of Two-Stage X-Band Power Amplifier Using GaN-HEMT

This paper presents an X-band two-stage power amplifier using GaN-HEMT. Two-stage structure was adopted to take its high gain and simple inter-stage matching network. Based on a 3D EM simulation, the bond-wire inductance and the parasitic capacitance were predicted. By reducing bond-wire inductance, Q of the matching network is decreased and the bandwidth is improved. The implemented two-stage PA shows a power gain of more than 16 dB, saturated output power of more than 42.5 dBm, and a efficiency of more than 35 % in frequency range of 8.1~8.5 GHz with an operating voltage of 40 V.

Design of Two-Stage Fully-Integrated CMOS Power Amplifier for V-Band Applications

This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.