Joo-Hyung Chae

Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces

In this paper, we propose a dynamic comparator that improved the operation performance of receiver (RX) with the effort to reduce power consumption. It is implemented via double-tail StrongARM latch comparator with an active inductor and efforts are made to minimize power consumption for high-speed resulting in better energy efficiency at the targeted high frequency. In this regard, our comparator is suitable for memory application RX to satisfy both low-power and high-speed. It is applied to the single-ended RX designed with a continuous-time linear equalizer, a clock generator and a quarter-rate 2-tap decision-feedback equalizer which is appropriate for the high-frequency memory application. Compared to the conventional one, our design, fabricated in 55nm CMOS process, provides an improvement of 7% in unit interval (UI) margin under the same power consumption and receives up to 10Gb/s PRBS15 data at BER < 10-12 with 0.4 UI margin and energy efficiency of 0.67pJ/bit.

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication

In this paper, we propose a low power transceiver (TRx) suitable for a wired intra-body area network (BAN) communication. The proposed transceiver is designed with relaxation oscillator which is appropriate for this low frequency (< 50MHz) application. To lessen the complexity of building this BAN system, we use clock edge modulation (CEM) data as sending or receiving data, and this allows the transceiver to operate without reference clock. The relaxation oscillator in this transceiver is designed to be able to generate CEM data pattern as well as a clock, so this can minimize power consumption in designing additional block related to transmission. Proposed circuit operates up to 36MHz with 1.0V supply voltage. It consumes 1.26uW at an input data rate of 10Mbps and achieves 0.13pJ/bit of energy per bit even though the circuit is implemented in a 0.18µm CMOS technology.

A 1.74mW/GHz 0.11–2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

A 180° phase-shift digital delay-locked loop (DLL) for LPDDR4 memory controllers is composed of a global DLL and a local DLL for each channel. The global DLL uses a time-to-digital converter to achieve fast-locking, and then shuts down to reduce power consumption. The local DLL, locking based on delay codes from the global DLL, uses a digital window phase detector (PD) and tracks the input clock phase to compensate for process, voltage, and temperature variations. Repeatedly controlled window size of the digital window PD in this local DLL reduces the high-frequency jitter compared to the DLL using bang-bang PD. Implemented in 65nm CMOS process, proposed digital DLL dissipates 1.74mW/GHz and occupies 0.074mm2. It operates over a frequency range of 0.11-2.5GHz, and locks within 6 cycles at 0.11GHz and within 17 cycles at 2.5GHz. At 2.5GHz, the integrated jitter of the DLL output clock with the digital window PD is 953fsrms and the long-term jitter of it is 2.64psrms and 20.6pspp.