Hankyu Chi

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~1550 nm

We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10(-12) bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of -11 dBm, -8 dBm, and -2 dBm for data rates of 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10(-12). The measured energy efficiency of the Si-photonic receiver is 2.6 pJ/bit at 25 Gb/s with an optical input power of -11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of -2 dBm. The hybrid-integrated silicon photonic transmitter, comprised of a depletion-type Mach-Zehnder modulator (MZM) and a CMOS driver circuit (CMOS Tx IC), shows better than 5.7 dB extinction ratio (ER) for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10(-15) BER at 25 Gb/s, 10(-14) BER at 28 Gb/s, and 6 x 10(-13) BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-㎚ CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9?28 inch Nelco4000-6 microstrips at 4?7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 ㎟ and consumes 69.8 ㎽, while the rest of the receiver occupies 0.297 ㎟ and consumes 56.0 ㎽ at the 7-Gb/s data-rate and supply voltage of 1.35 V.

A 40-Gb/s transceiver in 0.13-μm CMOS technology

A fully integrated 40-Gb/s transceiver is implemented in a 0.13-mum CMOS technology. This paper describes the challenges in designing a 20-GHz input sampler, a 20-GHz quadrature LC-VCO, a 20-GHz bang-bang phase detector, and a 40-Gb/s equalizer. The transceiver occupies 1.7 times 2.9 mm2 and dissipates 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 215-1 PRBS data is 1.85 psrms over a wire-bonded plastic ball grid array (PBGA) package, an 8-mm RO-4350B PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable, while the recovered clock jitter is 1.77 psrms. The measured BER is < 10-14.

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS

This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in the limiting amplifier (LA) for bandwidth extension. The combined TIA and LA block exhibits a transimpedance gain of 78 dBΩ and a bandwidth of 11 GHz. The TIA and the LA block consume 1.3 mA and 24 mA at 1 V supply voltage, respectively.

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Abstract—We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively. Index Terms—Digitally controlled oscillator, ring oscillator, PVT compensated DCO, PT-counteracting voltage regulator, all-digital phase-locked loop

A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier

This paper describes the design and performance of a 10-Gb/s optical receiver front-end fabricated in a 0.13-μm CMOS technology. To realize a wide bandwidth transimpedance amplifier (TIA) that has large input parasitic capacitance, an area-efficient stacked spiral transformer is implemented. By using a capacitance multiplication technique, the baseline wander resulting from a current offset cancellation is minimized. The TIA achieves a transimpedance gain of 58.5dB£i, an area of 0.02mm2, and a bandwidth of 7.9GHz. The limiting amplifiers (LAs) following the TIA use negative impedance converters to enhance the bandwidth. The TIA and the LAs consume 5mW and 28.4mW, respectively with a supply voltage of 1.2V.

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

This paper describes a reset-free delaylocked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop’s lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-㎛ CMOS process, postlayout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 ㎒. It occupies 0.04 ㎟ and dissipates 16.6 ㎽ at 1.2 ㎓.

A clock synchronization system with IEEE 1588–2008 adapters over existing Gigabit Ethernet equipment

This paper presents an IEEE 1588–2008 adapter that provides existing Gigabit Ethernet equipment with the functionalities required to clock synchronization on the order of sub-microsecond. To compensate the time error caused by the queuing delays in the Gigabit Ethernet equipment, the adapter measures the residence time and runs the peer delay mechanism for the equipment. Major functional blocks including the clock synchronization cores, Media Access Controls (MACs), and frame buffers have been integrated into a 21 mm2 silicon chip in 0.18 μm CMOS process. Experimental results show that the end devices can be synchronized within ±20 ns by simply attaching the proposed IEEE 1588–2008 adapters to the ordinary switches that connects the end devices.

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology

This paper describes a design methodology for CMOS silicon photonic interconnect ICs according to CMOS technology scaling. As the CMOS process is scaled, the endurable voltage stress and the intrinsic gain of the CMOS devices are reduced; therefore, a design of the highswing transmitter and high-gain receiver required at the silicon photonic interface becomes much more challenging. In this paper, a triple-stacked Mach-Zehnder modulator driver and an inverter-based transimpedance amplifier with inductive feedback are proposed, and the robustness of the proposed designs is verified through Monte Carlo analyses. The prototype ICs are fabricated using a 65-nm CMOS technology. The transmitter exhibits a 6 Vpp output swing, 98-mW power consumption, and 0.04-mm2 active area at 10 Gb/s. The receiver was verified with a commercial photodetector, and it exhibits a 78-dBΩ gain, 25.3-mW power consumption, and 0.18-mm2 active area at 20 Gb/s.