Joo-On Park

A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer inspection

The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing, yet little data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63/cm2. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

The analysis of EUV mask defects using a wafer defect inspection system

EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still critical challenges for EUVL to address to become a mature technology like todays litho workhorse, ArF immersion. Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the requirement as of today. In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for detection of phase defects on the mask. A previous study suggested that EUVL requires better defect inspection sensitivity than optical lithography because EUVL will print smaller defects. Improving the defect detection capability involves not only inspection system but also wafer preparation. A few parameters on the wafer, including LWR and wafer stack material and thickness are investigated, with a goal of enhancing the defect capture rate for after development inspection (ADI) and after cleaning inspection (ACI). In addition to defect sensitivity an overall defect control methodology will be suggested, involving mask, mask inspection, wafer print and wafer inspection.

Properties of EUVL masks as a function of capping layer and absorber stack structures

We have fabricated extreme ultraviolet lithography (EUVL) blank masks consisting of a TaN absorber, Ru capping layer, and Mo/Si multilayers using ion-beam sputter deposition and investigated their dependence on capping layer and absorber stack structure. At EUV wavelengths, the reflectivities of the multilayers, including their dependency on the thickness of the capping and absorber layers, are in good agreement with simulation results obtained using Maxwell equations and the refractive indexes of each layer. Ru, one of the most promising capping materials on Mo/Si multilayers due to its resistance to oxidation and selectivity to etching, also shows better EUV reflectivity than Si as a capping layer if we choose a thickness that produces a constructive interference. To meet the reflectivity requirements (⩽ 0.5 %) in the SEMI EUVL mask standard specifications, a TaN absorber at least 70 nm thick should be applied. However, aerial image results simulated by using EM-Suite show that 40 nm is sufficient for the TaN absorber to display the maximum image contrast. In addition, horizontal-vertical (HV) biasing effects due to mask shadowing become negligible if the TaN is reduced to about 40 nm. As a result, we suggest using a thin TaN absorber 40 nm thick since it is able to minimize mask shadowing effects without a loss of image contrast.

Assessment of EUV resist readiness for 32-nm hp manufacturing and extendibility study of EUV ADT using state-of-the-art resist

Extreme ultraviolet lithography (EUVL) is the most effective way to print sub-32 nm features. We have assessed EUVL resist readiness for 32 nm half-pitch (HP) manufacturing, presenting process feasibility data such as resolution, depth of focus (DOF), line edge roughness/line width roughness (LER/LWR), mask error enhancement factor (MEEF), resist collapse, critical dimension (CD) uniformity, post-exposure delay (PED) stability, and post-exposure bake (PEB) sensitivity. Using the alpha demo tool (ADT), a full field ASML EUV scanner, we demonstrate the feasibility of a k1 ~0.593 resist process for 32 nm HP line/space (L/S) patterning. Exposure latitude (EL) was 13% at best focus, and DOF was 160 nm at best dose using a 60 nm thick resist. By incorporating a spin-on underlayer, the process margin could be improved to 18.5% EL and 200 nm DOF. We also demonstrate ADT extendibility using a state-of-the-art EUV platform. A k1 ~0.556 resist process was demonstrated for 30 nm HP L/S patterns, providing a 13% EL, 160 nm DOF, and a common process window with isolated lines. 28 nm HP patterning for a k1 ~0.528 resist process could be feasible using a more advanced resist with improved DOF and resist collapse margin.

Progress in EUV lithography toward manufacturing

In this article the recent progress in the elements of EUV lithography is presented. Source power around 205W was demonstrated and further scaling up is going on, which is expected to be implemented in the field within 2017. Source availability keeps improving especially due to the introduction of new droplet generator but collector lifetime needs to be verified at each power level. Mask blank defect satisfied the HVM goal. Resist meets the requirements of development purposes and dose needs to be reduced further to satisfy the productivity demand. Pellicle, where both the high transmittance and long lifetime are demanded, needs improvements especially in pellicle membrane. Potential issues in high-NA EUV are discussed including resist, small DOF, stitching, mask infrastructure, whose solutions need to be prepared timely in addition to high-NA exposure tool to enable this technology.

Methodology of flare modeling and compensation in EUVL

Flare in EUV mirror optics has been reported to be very high and long range effect due to its character which is inversely proportional to the 4th order of wavelength. The high level of flare will generate CD (Critical Dimension) variation problem in the area where the gradient of aerial pattern density is large while the long range influencing character would confront an issue of computational challenge either for OPC (Optical Proximity Correction) modeling or for any other practical ways to accommodate such a long range effect. There also exists another substantial challenge of measuring and characterizing such a long range flare accurately enough so that the characterized flare can successfully be used for the compensation in the standard OPC flow.

The application of EUV lithography for 40nm node DRAM device and beyond

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography technology for the 32 nm half-pitch node and beyond. We have evaluated the Alpha Demo Tool(ADT) characterizing for mixed-andmatched overlay(MMO), flare noise, and resolution limit. For process integration, one of the important things in EUVL is overlay capability. We performed an overlay matching test of a 1.35NA and 193 immersion tool using a low thermal expansion material(LTEM) mask. We also investigated the flare level of the EUV ADT for device applications. The current EUV tool has a higher flare level than ArF lithography tools. We applied a contact layer for 40nm node device integration to reduce the variation in critical dimension(CD) from the flare noise.

Assessments on process parameters' influences to the proximity correction

The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.

Printability and Inspectability of Defects on the EUV Mask for sub32nm Half Pitch HVM Application

The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing, yet little data is available for understanding native defects on real masks. In this paper, a full field EUV mask is fabricated to see the printability of various defects on the mask. Programmed pit defect shows that minimum printable size of pits could be 17 nm of SEVD from the AIT. However 23.1nm in SEVD is printable from the EUV ADT. Defect printability and identification of its source along from blank fabrication to mask fabrication were studied using various inspection tools. Capture ratio of smallest printable defects was improved to 80% using optimized stack of metrical on wafer and state-of-art wafer inspection tool. Requirement of defect mitigation technology using fiducial mark are defined.

A 35-GHz radar for sensing applications

We report a millimeter-wave stepped-frequency radar operating from 29.72 to 37.7 GHz for sensing applications. The radar is implemented using coherent super-heterodyne scheme and completely realized using microwave and millimeterwave integrated circuits. The developed radar has been demonstrated for different sensing applications with high accuracy and resolution. It can be used for various sensing applications including pavement and bridge assessment, liquid-level measurement, detection and location of buried mines and unexploded ordnance (UXO), detection of intrusion to structures including important civil facilities, detection of slow moving objects, surveillance and monitoring of hidden activities and objects.