Sung-Gon Jung

Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

Abstract. We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.

E-beam writing time improvement for Inverse Lithography Technology mask for full-chip

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k1 lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[4,5], it has been shown that the Inverse Synthesizer (ISTM) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.

Effectiveness and confirmation of local area flare measurement method in various pattern layouts

It is well known that flare, which increases the background intensity and loses the image contrast, degrades the pattern fidelity and CD uniformity. Usually there is little mid and long-range flare at the initial exposure tool introduction except the short-range flare, so called, aberration. However, flare effect is observed in used exposure tools. To estimate the influence of flare, both lens quality of the exposure tool and mask pattern layout with various open ratios are important parameters to be considered. So it is very crucial to make a standard mask layout to measure the flare value as a tool specification. So far, CD variation of the long-range flare has been measured and reported. The long-range flare includes the average influence of the short and mid-range flare and affects more than several hundred- micron distances. Recently it is observed that lens contamination is a dominant component among sources of flare and induced by the pattern layout with its different open ratio. Being contaminated, the lens malfunctions with various types of scattering sources. These scattering sources make the mid and long range flare. This type of flare source has time dependence. If there are proper monitoring methods for the flare measurement, it is possible to maintain the lens quality within the limit of mid range flare. In addition, matching the flare value to CD distribution is not easy because there is no standard measurement method to distinguish the short and mid-range flare from the long-range one. In this paper a LOcal Area Flare Evaluation Reticle (LOAFER) method is suggested. The LOAFER is designed to measure the local area flare of the lens, that is, the short and mid-range flare and the local flare distribution of the exposure tool lens can be characterized. Then matching the result to the real device pattern will be introduced.

Hotspot fixing using ILT

For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the layout. The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.

Comparison of double patterning technologies in NAND flash memory with sub-30nm node

Fine patterning technologies - E-beam lithography, SPT (Spacer Patterning Technology) and SaDPT (Self aligned Double Patterning Technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NAND Flash memories, the merits and demerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF(Charge Trap Flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.

Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT

Design for Manufacturing (DFM) is being widely accepted as one of keywords in cutting edge lithography and OPC technologies. Although DFM seems to stem from designers intensions to consider manufacturability and ultimately improve the yield, it must be well understood first by lithographers who have the responsibility of reliable printing for a given design on a wafer. Current lithographers understanding of DFM can be thought of as a process worthy design, and the requirements set forth from this understanding needs to be well defined to a designer and fed forward as a necessary condition for a robust design. Provided that these rules are followed, a robust and process worthy design can be achieved as a result of such win-win feed-forward strategy. In this paper, we discuss a method on how to fully analyze a given design and determine whether it is process worthy, in other words DFM-worthy or not. Mask Error Enhancement Factor (MEEF), Through Focus MEEF (TF-MEEF) and Mean-To-Target (MTT) values for an initial tentative design provide good metrics to obtain a robust and process worthy design. Two remedies can be chosen as DFM solutions according to the aforementioned analysis results: modify the original design or manipulate the layout within a design tolerance during OPC. We will discuss on how to visualize the analyzed results for the robust and process worthy OPC with some relevant examples. In our discussions, however, we assumed that the robust model be being used for each design verification, and such a model derived with more physical parameters that correlates better to real exposure behavior. The DFM can be viewed as flattening the TF-MEEF across the design.

Assessments on process parameters' influences to the proximity correction

The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.

Improving model prediction accuracy for ILT with aggressive SRAFs

For semiconductor IC manufacturing at sub-30nm and beyond, aggressive SRAFs are necessary to ensure sufficient process window and yield. Models used for full chip Inverse Lithography Technology (ILT) or OPC with aggressive SRAFs must predict both CDs and sidelobes accurately. Empirical models are traditionally designed to fit SEMmeasured CDs, but may not extrapolate accurately enough for patterns not included in their calibration. This is particularly important when using aggressive SRAFs, because adjusting an empirical parameter to improve fit to CDSEM measurements of calibration patterns may worsen the models ability to predict sidelobes reliably. Proper choice of the physical phenomena to include in the model can improve its ability to predict sidelobes as well as CDs of critical patterns on real design layouts. In the work presented here, we examine the effects of modeling certain chemical processes in resist. We compare how a model used for ILT fits SEM CD measurements and predicts sidelobes for patterns with aggressive SRAFs, with and without these physically-based modeling features. In addition to statistics from fits to the calibration data, the comparison includes hot-spot checks performed with independent OPC verification software, and SEM measurements of on-chip CD variation using masks created with ILT.

Improving model-based OPC performance for sub-60nm devices using real source optical model

In order to satisfy high density and cost effective production, extreme illumination condition, maximum sigma and OAI, is currently implemented at low k1 process. In this condition, minimal change of optical condition results in large difference of patterning. Specifically, blurring, intensity asymmetry and tele-centricity of illumination source cause deformation of some pitch patterns and CD asymmetry of semi-isolated patterns. In conventional modeling using ideal source optical model such as top-hat shape or profile, those data are regarded as noise terms since it is difficult to fit them well and such model inaccuracy produce OPC error. This paper provided results of the OPC performance using real source optical model obtained from a scanner. Real source image was filtered and normalized for easy handling. It was shown that we improved the model accuracy and significantly reduced the number of parameters. As a result, we increased process margin for sub-60nm device.

AF Fixer : New incremental OPC method for optimizing Assist Feature

Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AFs print more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present, mask manufacturers must downsize AFs below 30nm to solve this problem. This is challenging and increases mask cost. We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in terms of DOF after OPC. We have devised an effective algorithm that removes printing AFs. It can not only search for the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF printing problems economically and accurately.