Joo-young Lee

A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs

Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by trap-assisted gate-induced drain leakage currents depending on trap energy dispersion. Through analyses of full chip retention failure curves and interface trap density ( Dit*) measurements, we propose that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale. As a result, the retention time is eventually to be determined by the main distribution function only.

Novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI for the improvement of data retention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-/spl mu/m technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si/sub 3/N/sub 4/-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-/spl mu/m technology and beyond.

Enhancement of light-extraction efficiency of organic light-emitting diodes using silica nanoparticles embedded in TiO 2 matrices

We investigate two types of internal light-extraction layer structures for organic light-emitting diodes (OLEDs) that consist of silica nanoparticles (NPs) embedded in high-refractive-index TiO₂ matrices. The composite of silica NPs and TiO₂ matrices was coated on the glass substrate and fabricated with and without a SiO₂ planarization layer. An increase in the optical out-coupling efficiency by a factor of 2.0 was obtained at a high luminance of 3,000 cd/m² from OLEDs containing the silica NPs embedded in TiO₂ matrices between glass substrates and Zn-doped In₂O₃ (IZO) electrodes after additional planarization processes. This is consistent with the analytical result using the finite-difference time-domain (FDTD) method. Randomly distributed silica NPs acting as scattering centers could reduce the optical loss when extracting light. By using additional planarization processes with a PECVD-derived SiO₂ layer, one can assure that smoother surfaces provide higher out-coupling efficiency, which attain 100% and 97% enhancements in power (lm/W) and current (cd/A) efficiencies, respectively.

Extending the DRAM and FLASH memory technologies to 10nm and beyond

Memory devices such as DRAM and NAND flash will continue to increase their capacity through scaling, which will extend to below the 10nm regime. From a device physics perspective, there are possible solutions for scaling below 10nm. However, the challenges of sub-10nm scaling will come from the productivity. In fact, major challenges for the realization of high density memory devices are lithography and vertical etching of high aspect ratio holes in DRAM and 3D flash memories. Here, status and the direction of DRAM and flash memory scaling technologies will be reviewed with a special focus on the extendibility from not only device physics but also productivity points of view.

23.2: Optical Performance Analysis Method of Auto-stereoscopic 3D Displays

In this paper, we investigated performance analysis methods of auto-stereoscopic 3D displays in an optical point of view. This paper provides optical measurement and analysis methods for auto-stereoscopic displays. Issues discussed include: (1) optimum viewing distance; (2) luminance & contrast ratio; (3) color performance; (4) 3D point crosstalk; (5) spatial crosstalk; (6) ortho-stereoscopy angle/pseudo-stereoscopy angle; (7) luminance difference ratio.

The cell pattern correction through design-based metrology

Starting with the sub 2Xnm node, the process window becomes smaller and tighter than before. Pattern related error budget is required for accurate critical-dimension control of Cell layers. Therefore, lithography has been faced with its various difficulties, such as weird distribution, overlay error, patterning difficulty etc. The distribution of cell pattern and overlay management are the most important factors in DRAM field. We had been experiencing that the fatal risk is caused by the patterns located in the tail of the distribution. The overlay also induces the various defect sources and misalignment issues. Even though we knew that these elements are important, we could not classify the defect type of Cell patterns. Because there is no way to gather massive small pattern CD samples in cell unit block and to compare layout with cell patterns by the CD-SEM. The CD- SEM is used in order to gather these data through high resolution, but CD-SEM takes long time to inspect and extract data because it measures the small FOV. (Field Of View) However, the NGR(E-beam tool) provides high speed with large FOV and high resolution. Also, it’s possible to measure an accurate overlay between the target layout and cell patterns because they provide DBM. (Design Based Metrology) By using massive measured data, we extract the result that it is persuasive by applying the various analysis techniques, as cell distribution and defects, the pattern overlay error correction etc. We introduce how to correct cell pattern, by using the DBM measurement, and new analysis methods.

17.2: Advanced Display Motion Induced Color Distortion and Crosstalk Analysis Methods

Motion artifact of Display devices has a huge interest from industries and users recently. Among those artifacts, color break up (CBU) and Dynamic false contour are the main degrading characteristic in field sequential type displays and Plasma Displays. Also, motion blur has been researched intensively recently, but there is a critical motion induced artifact due to phosphor or LC unwanted performance. This visual phenomenon is similar to normal crosstalk artifact, so it is named as motion crosstalk. Unfortunately, there are no objective measurement methods for those two motion-induced artifacts. Here we introduce advanced analysis methods for two different kinds of motion artifacts.

Extracting accurate position and energy level of oxide trap generating random telegraph noise(RTN) in recessed channel MOSFET's

In this paper, we have proposed an extraction method to find accurate oxide trap locations and energy level in recessed channel structure such as SRCAT. Analytical models for poly depletion effect and the surface potential variation in the cylindrical coordinate were derived and applied to DRAM SRCAT.

A study of reticle CD behavior for inter-area pattern loading difference

We can control the pattern on wafer without optimization of layout design if we understand reticle cd behavior