Joo-Yul Park

Memory efficient multi-rate regular LDPC decoder for CMMB

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys¿ Design Compiler using Chartered 0.18 ¿m CMOS cell library. The synthesized design has the gate size of 455 K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

Parallel LDPC decoding using CUDA and OpenMP

Digital mobile communication technologies, such as next generation mobile communication and mobile TV, are rapidly advancing. Hardware designs to provide baseband processing of new protocol standards are being actively attempted, because of concurrently emerging multiple standards and diverse needs on device functions, hardware-only implementation may have reached a limit. To overcome this challenge, digital communication system designs are adopting software solutions that use central processing units or graphics processing units (GPUs) to implement communication protocols. In this article we propose a parallel software implementation of low density parity check decoding algorithms, and we use a multi-core processor and a GPU to achieve both flexibility and high performance. Specifically, we use OpenMP for parallelizing software on a multi-core processor and Compute Unified Device Architecture (CUDA) for parallel software running on a GPU. We process information on H-matrices using OpenMP pragmas on a multi-core processor and execute decoding algorithms in parallel using CUDA on a GPU. We evaluated the performance of the proposed implementation with respect to two different code rates for the China Multimedia Mobile Broadcasting (CMMB) standard, and we verified that the proposed implementation satisfies the CMMB bandwidth requirement.

An adaptive low-power LDPC decoder using SNR estimation

Owing to advancement in 4 G mobile communication and mobile TV, the throughput requirement in digital communication has been increasing rapidly. Thus, the need for efficient error-correcting codes is increasing. Furthermore, since most mobile devices operate with limited battery power, low-power communication techniques are attracting considerable attention lately. In this article, we propose a novel low-power, low-density parity check (LDPC) decoder. The LDPC code is one of the most common error-correcting codes. In mobile TV, SNR estimation is required for the adaptive coding and modulation technique. We apply the SNR estimation result to the proposed LDPC decoding to minimize power consumption due to unnecessary operations. The SNR estimation value is used for predicting the iteration count until the completion of the successful LDPC decoding. When the SNR value is low, we omit computing the parity check and the tentative decision. We implemented the proposed decoder which is capable of adaptively skipping unnecessary operations based on the SNR estimation. The power consumption was measured to show the efficiency of our approach. We verified that, by using our proposed method, power consumption is reduced by 10% for the SNR range of 1.5-2.5 dB.

LDPC decoding for CMMB utilizing OpenMP and CUDA parallelization

As the 4G mobile communication systems require high transmission rate with reliability, the demand for efficient error correcting code increases. In this paper, a novel LDPC (Low Density Parity Check) decoding method is introduced. We address a parallel software implementation of LDPC decoding for CMMB (China Multimedia Mobile Broadcasting) standard. LDPC codes for CMMB employ a regular H-matrix which has the fixed row and column weights. While effectively utilizing the regularity of the H-matrix, we process information on H-matrices for multiple code rates using OpenMP pragmas on a multi-core processor and execute the decoding algorithm in parallel using CUDA (Compute Unified Device Architecture) on a GPU (Graphics Processing Unit). We evaluated the performance of the proposed implementation with respect to two different code rates, and verified that the proposed implementation satisfies the bandwidth requirement for CMMB.

Design of Low Power MAC Operator with Dual Precision Mode

MAC (multiply and accumulate) operations are heavily involved in many DSP applications. To improve the performance of MAC operations, it is very crucial to make multiplication fast. In this paper, we propose a set of novel MAC operator designs with constant coefficients. It is well-known that shifting can replace a constant multiplication if the constant is a power of 2. We extend this idea in such a way that by employing more than 2 barrel shifters and a supplementary multiplier we can design a very efficient constant multiplier for general constants. To enhance the applicability of our design for a wide range of constants, a support for variable precision computations has been implemented. Experimental results show that our designs achieve consistent enhancement in terms of power consumption when our design is com pared with other existing optimized designs.

Overlapped message passing technique with resource sharing for high speed CMMB LDPC decoder

Today, demands for high speed digital communication are getting bigger due to wide deployment of 4G mobile communications and mobile TV services. Requirement for high speed data processing makes forward error correction crucial. LDPC is one of the most popular error correcting codes. In this paper, we propose a novel LDPC decoder for the China Multimedia Mobile Broadcasting (CMMB) standard. The LDPC decoding is carried out iteratively, which leads to relatively long decoding latency. Also, due to long code words, the amount of required memory is huge. To resolve these issues, we propose a novel Overlapped Message Passing (OMP) algorithm with an efficient resource sharing technique. Using the proposed method, we find the best permuted parity check matrix of the CMMB to improve the throughput while minimizing the memory requirement. Using the OMP algorithm only, we could improve the performance by 10%. To avoid potential memory access conflicts, a memory grouping technique to improve pipelining performance is also proposed. By applying all the techniques that we propose in this paper, we could improve the performance up to by 451.

Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation

In this paper, we propose a low-power adaptive low-density parity check (LDPC) decoder that utilizes dynamic voltage and frequency scaling to reduce power consumption. Most existing adaptive LDPC decoders have focused only on the decoding performance based on the signal-to-noise ratio (SNR) estimation. However, significant idle power is consumed when the decoder awaits the next frame after processing a frame. In mobile communication standards such as China Mobile Multimedia Broadcasting and Digital Video Broadcasting Satellite Second Generation, adaptive coding and modulation has been adopted. Thus, it is possible to reduce the power consumption efficiently by using the SNR estimation. In this paper, we apply a customized frequency selection scheme and a variable voltage generation scheme to an adaptive LDPC decoder to reduce the dynamic power consumption. The proposed schemes result in a reduction of 44% in the energy consumption of an LDPC decoder implemented using 0.18-μm complementary metal-oxide-semiconductor technology.