Hyung-Gu Park

A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc-dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the ac input voltage. The delay between the ac input current and the ac input voltage due to the delays of internal blocks such as voltage limiter, level shifter, gate driver, and comparator will cause the reverse leakage current, degrading the power efficiency. Thus, the proposed active rectifier adopts the DLL to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, negative impedance circuit (NIC) is also adopted to minimize switching loss. In the case of dc-dc converter, phase-locked loop is adopted for the constant switching frequency in process, voltage, and temperature (PVT) variation to solve the efficiency reduction problem, especially by heat. This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm × 3.5 mm. When the magnitude of the ac input voltage is 8.95 V, the maximum efficiencies of the proposed active rectifier and dc-dc converter are 91.5% and 92.7%, respectively. The range of ac input voltage is 3-20 V, and the efficiency of the WPRU is about 80.86%.

Wide input range, high-efficiency magnetic resonant wireless power receiver

This article presents a full-CMOS receiver for magnetic resonant wireless battery charging system. A wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, one-stage voltage multiplier or two-stage voltage multiplier mode. As a result, a rectified DC output voltage is from 7.5 to 19 V for an input AC voltage of 5–20 V. This chip is implemented using 0.35 μm BCD technology with an active area of around 5 × 2.5 mm2. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94%.The efficiency of the receiver is about 60% when the distance between the transmitter and receiver is about 1 m.

A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS

This brief presents a wide-locking-range injection-locked frequency divider (ILFD) that uses an automatic frequency calibration loop. The proposed ILFD uses the ring oscillator to provide the high division ratio with small chip area. A dual-injection scheme is proposed in order to achieve the wide locking range of the ILFD. The free-running frequency of the ILFD is automatically digitally calibrated to reflect the frequency of the injected signal from the voltage-controlled oscillator. To control the frequency of the ILFD, the load current is digitally tuned with 3-bit control signal. The ILFD is fabricated using 65-nm CMOS process, and by tuning the load current, it achieves the wide operation frequency range of 14.1-45.8 GHz. When the input signal of 30 GHz is injected, the locking range of the ILFD is 7.2 GHz, while the power consumption is 2.5 mW from a 1-V supply voltage.

A design of wide input range, high efficiency rectifier for mobile wireless charging receiver

This paper presents a high-efficiency Schottky diode rectifier for the mobile wireless charging receiver. A wide input range multi-mode rectifier is proposed for a magnetic resonant wireless charging system. The configuration is automatically changed based on the input AC voltage to widen the input voltage range. It is fabricated in a 0.35 um BCD process and its area is 1mm×1.5mm. When the magnitude of the input power is 4 W at 128 kHz, the Power Conversion Efficiency of the multi-mode Schottky diode rectifier is 85%, which is improved by 10% compared with that of the full-wave MOSFET rectifier.

An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-

An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177- μW ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm × 4 mm and that of the PLL is 0.4 mm × 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a frequency offset of 70 kHz and fluctuation of ±75 kHz (the maximum frequency error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 μW from a 1.2-V supply voltage.

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This paper presents a highly linear, small-area analog front end with gain and offset compensation for automotive capacitive pressure sensor. We propose a capacitance-tovoltage converter circuit that measures the capacitance value of the capacitive sensor with the high accuracy and linearity. In this paper, the linearity of the analog front end is guaranteed using full-analog gain and an offset calibration circuit. The proposed design is implemented using CMOS 0.35 μm technology with an active area of 1.94 mm x 1.94 mm. The full output range is from 0.5 to 4.5 V. The ratiometricity is within ±0.7% when the supply voltage is changed by ±10%. The power consumption is 25 mW from a 5 V supply. The output accuracy is within ±1% with respect to Process, Voltage, Temperature variations.

W Leakage-Compensated PLL and Automatic Quench Waveform Generator

This paper presents a small area LC VCO with an on-chip 3-D solenoid inductor using the 0.13 m digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. The LC VCO with solenoid inductor is fabricated in 0.13 m process and the die area of solenoid inductor is 0.013 mm2. The measured phase noise is -110.61 dBc/Hz at 1MHz offset when the output frequency is 5.195 GHz. The measured tuning range is about 1.1 GHz. The power consumed from 1.2 V supply, is 13.2 mW.

A Highly Linear, Small-Area Analog Front End With Gain and Offset Compensation for Automotive Capacitive Pressure Sensors in 0.35- m CMOS

Abstract Qi, the wireless power standard, has been proposed to allow low power systems to receive power through wireless inductive power transfer. The standard outlines the essential, desired and optional requirements for developing the wireless power transfer platform. In this paper, we present the design and implementation results of communication controller for guided positioning single transmitter–single receiver wireless power transfer platform. Apart from the basic design, additional processing and data storage capability is introduced to make the design adaptive in terms of response time and the size of control data transfer. The method of estimating the amount of power transfer is modified to reduce design complexity and internal power consumption of power transmitter and receiver. The implementation results help to access the ratio of power transferred to resource utilization and the ratio of power transferred to power consumed in simplistic wireless power transfer platform.

A 4.1–5.2 GHz LC VCO using a vertical solenoid inductor in 0.13 μm digital CMOS

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and I2C for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 mm2.

Communication controller and control unit design for Qi wireless power transfer

This paper presents a DC-DC buck converter with Phase-Locked Loop (PLL) to generate the constant switching frequency regardless of Process, Voltage, Temperature (PVT) variations. When the input range is from 8 V to 20 V, the proposed DC-DC buck converter with PLL is implemented to have over 90% efficiency in heavy load current of 1.0 A. also to reduce the size of the external device while maintaining high efficiency, 2 MHz switching frequency and 2.2 μH inductance were used. The proposed DC-DC buck converter with PLL to generate constant frequency to compensate for the efficiency variation. As a result, the efficiency variation is less than 1%. This chip was fabricated using 0.18 μm BCD technology, and the area is 3.96 mm2. The maximum efficiency of proposed DC-DC buck converter with PLL is 92.53%.