Joong-hyun Baek

Thermal characterization of high performance MCP with silicon spacer having low thermal impedance

This paper presents the thermal optimization of a thermally enhanced FBGA MCP (multichip package). Because of insufficient heat path from top chip to PCB, heat is trapped between chips as shown in computer simulations. To solve the heat trap problem, we designed and developed a thermally enhanced MCP with a silicon spacer, which was applied to a 144 FBGA MCP. An experiment was carried out to verify the thermal characteristics of the thermally enhanced MCP, concerning structural variation and replacement of the adhesive. The experimental results showed that the thermal resistance of the MCP is improved and the low thermal conductive adhesive material is an important heat path barrier.

Optimization of TAB inner lead bonding process

Delamination has occurred at the adhesive which is subject to thermal damage. The heat from the hot bonding tool transfers to the adhesive through the leadframe and degrades the thermally weak adhesive during the TAB ILB (inner lead bonding) process. It is essential to retain the temperature at the adhesive below its degradation temperature. In this study, the effect of the temperature of the heat cartridge in the bonding tool and the dwell time on degradation of the adhesive was investigated, using finite volume method. As a result, the optimized process condition avoiding degradation of the adhesive was proposed. In addition, the effect of this temperature on bondability of the Au bump was also taken into consideration.

Thermal Characteristics of Chip Stack and Package Stack Memory Devices in the Component and Module Level

The demand of the high storage memory is providing a momentum for stacking technology in DRAM industry. As the stack technology is developed, more heat sources are embedded in the same package footprint and increase the device temperature. Therefore, the thermal management is one of most important issues in DRAM stack package. Since the chip stack and package stack technology are competing each other as a solution of DRAM stack, it is necessary to characterize thermal behavior of each package for better thermal management. Hence, in this paper, the authors studied the thermal performance characteristics of chip stack and package stack package in component and module level. The study is focused on the dual stack, which is most demanded stack height in DRAM market. The test package and module was assembled with the thermal test die and the DRAM junction temperature was measured to compare the thermal performance. The package stack package showed better thermal performance in component level because of its larger package size. On the other hand, the chip stack package showed better thermal performance in module level when the heat sink is used.

Thermal management of high power memory module

In the semiconductor industry, the memory device has not been considered as a high power consuming product. However, the increase in the market requirements for high speed and high density has resulted in memory devices that consume more power. Especially, a memory module accommodated with many high speed memory devices can reach to very high levels of power consumption, which in turn, can reach to very high junction temperatures. Therefore, the devices can not be operated properly without thermal management. Hence, in this paper, we are looking for a way to manage the heat generated in a high power memory module. To achieve this goal, a plate fin type heat sink based on air cooling was adopted with consideration of constraints related to the implementation of its thermal solutions. Then, the cooling capability of the memory module was estimated by a parametric study. The parametric study shows that a 20mm module pitch is necessary to dissipate the amount of heat that is targeted in this paper, which is 30W. With the 20mm module pitch, an optimized heat sink configuration was designed by simulation and the cooling performance of the designed heat sink was validated by experiments. For the experiment, test modules were assembled and the junction temperatures of memory devices mounted on modules was measured on a test board. The results showed that simulated and measured data well correlate with each other within acceptable ranges. The maximum cooling capability of the designed heat sink is 37.1W with a 20mm module pitch

Junction-to-top and junction-to-board thermal resistance measurement for 119 BGA packages

Junction-to-top (/spl theta//sub jt/) and junction-to-board (/spl theta//sub jb/) thermal resistance of a 119 BGA package for 4 Mbit SP SRAM have been investigated using the cold plate-Teflon block method and was compared with the junction-to-case thermal resistance (/spl theta//sub jc/) measurement method. Both thermal dice and real dice were prepared to measure the 119 BGA package thermal resistance. The junction-to-case and junction-to-top thermal resistance for a real die are about 3.5/spl deg/C/W and 3.8/spl deg/C/W respectively, whereas with a thermal die, the junction-to-case and junction-to-top thermal resistance are 4.0/spl deg/C/W and 4.8/spl deg/C/W respectively. For both thermal and real die, the junction-to-case thermal resistance is less than the junction-to-top thermal resistance. This is attributed to the different thermal boundary conditions applied to the 119 BGA package for each test method. In the meantime, thermal resistances of packages with thermal dice were approximately 14.3/spl sim/26.3% higher than those of package with real dice, the reason for which is being investigated.

Thermal characterization of a 3-dimensional memory module

SAMSUNG Electronics Co. has developed a 3-D memory module technique using a conventional assembly process for plastic package to get improved electrical performance, greater packaging density, and lower system weight and volume. This paper describes the thermal measurement and modeling result performed to determine the maximum junction temperature variation with the number of stacked packages and temperature distributions within 3-D modules. The effect of packaging materials on 3-D modules thermal performance is also presented.

Thermal characterization of high speed DDR devices in system environments [DRAM modules]

This paper studies the thermal characteristics of various memory modules for desktop and server systems. Using a CFD (computational fluid dynamics) simulator, we simulated these modules to predict their junction temperature. A detailed simulation model and power calculation procedures are described. Simulation results are provided for different conditions and parameter variations. Also, thermal measurements of these modules were carried out in real systems. The simulation and measured data were compared, and the results proved that the simulation model was sufficiently accurate for use in memory subsystem thermal design. Using the proposed simulation model of these modules and analysis results, the minimum requirements were defined for avoiding thermal problems in newly designed memory modules.

High thermal performance FBGA MCP with a silicon spacer

This paper presents the high thermal performance FBGA MCP (2 chips) using a silicon spacer. When many devices are integrated in a package, they consume much power and raise the junction temperature, so it is important for the package to have high thermal performance. Hence, we designed and developed a high thermal performance FBGA MCP with a silicon spacer that makes additional heat paths. With the silicon spacer, the thermal resistance of junction to ambient is improved by about 15% and the junction to junction is reduced by about 50%. To guarantee the package reliability of the package with the silicon spacer, we performed the reliability test in JEDEC level 3 condition and the package passed the test. The electrical reliability of the package was verified by measuring the diode voltage of the thermal test chip.

Micro cooling application on high density memory module

A numerical simulation and two kinds of experiments are conducted to investigate the thermal performance of several kinds of heat spreaders for high power memory modules. For numerical study, the commercial code, Flotherm, is used to model the 1GByte DDR memory module array. The convection heat transfer is analyzed for the memory module array with solid heat spreader under an airflow condition. For the wind runnel experiment, solid plate and block type spreaders are examined to obtain the thermal resistance of conjugate heat transfer of the solid under various airflow conditions. Also, to clarify the thermal characteristics and cooling capacity of liquid heat transport, newly designed liquid cooling devices, such as an embedded heat pipe spreader and vapor chamber with micro-wick structure are proposed and evaluated by the heat transport experiment with a water cold plate under the insulation condition.