Yun-Hyeok Im

Enhanced Boiling of a Dielectric Liquid on Copper Nanowire Surfaces

Copper nanowire arrays on a silicon (Si) substrate were fabricated by electro-chemical deposition through an anodic aluminum oxide (AAO) template to generate a high performance boiling surface. In this study, the pitch (~300 nm) and diameter (~200 nm) of the nanowires were fixed, and the height was varied between 1 and 8 μm. It is observed that copper nanowire surfaces increase the critical heat flux and reduce the incipience superheat compared to the baseline experiments, which were performed using a plain surface without nanowires. The work reported here is a major enhancement over previous studies on structured surfaces, which mainly considered structures which were on the order of 100 μm.

Flower-Like CuO Nanostructures for Enhanced Boiling

Flower-like CuO nanostructures were fabricated to enhance nucleate pool boiling. These nanostructures enhance boiling due to capillary wicking induced by their high surface area–to-volume ratio. Despite only having a thickness of 3–4 μm, ∼58% improvement in critical heat flux (CHF) was obtained by the addition of CuO nanostructures to both a smooth surface and a microgrooved surface. Because the CuO nanostructures are processed at room temperature, they can be easily combined with microfabricated cavities for additional boiling enhancement. Supplemental files are available for this article. Go to the publishers online edition of Nanoscale and Microscale Thermophysical Engineering to view the free supplemental file.

Pool Boiling of HFE 7200–C4H4F6O Mixture on Hybrid Micro-Nanostructured Surface

Steadily increasing heat dissipation in electronic devices has generated renewed interest in direct immersion cooling. The ideal heat transfer fluid for direct immersion cooling applications should be chemically and thermally stable, and compatible with the electronic components. These constraints have led to the use of Novec fluids and fluroinerts as coolants. Although these fluids are chemically stable and have low dielectric constants, they are plagued by poor thermal properties like low thermal conductivity (about twice that of air) and low specific heat (same as that of air). These factors necessitate the development of new heat transfer fluids with improved heat transfer properties and applicability. C 4 H 4 F 6 O is a new heat transfer fluid which has been identified using computer-aided molecular design (CAMD) and knowledge-based approaches. A mixture of Novec fluid (HFE 7200) with C 4 H 4 F 6 O is evaluated in this study. Pool boiling experiments are performed at saturated condition on a 10 mm x 10 mm silicon test chip with CuO nanostructures on a microgrooved surface, to investigate the thermal performance of this new fluid mixture. The mixture increased the critical heat flux moderately by 8.4% over pure HFE 7200. Additional investigation is necessary before C 4 H 4 F 6 O can be considered for immersion cooling applications.

Thermal characterization of high speed DDR devices in system environments [DRAM modules]

This paper studies the thermal characteristics of various memory modules for desktop and server systems. Using a CFD (computational fluid dynamics) simulator, we simulated these modules to predict their junction temperature. A detailed simulation model and power calculation procedures are described. Simulation results are provided for different conditions and parameter variations. Also, thermal measurements of these modules were carried out in real systems. The simulation and measured data were compared, and the results proved that the simulation model was sufficiently accurate for use in memory subsystem thermal design. Using the proposed simulation model of these modules and analysis results, the minimum requirements were defined for avoiding thermal problems in newly designed memory modules.

Development of Junction Temperature Decision (JTD) Map for Thermal Design of Nano-scale Devices Considering Leakage Power

As semiconductor technology keeps scaling down, leakage power grows significantly due to the reduction in threshold voltage, channel length, and gate oxide thickness. As the junction temperature increases in nano-scale devices, leakage power increases drastically. This phenomenon motivates the processor and package designers to take into account thermal effects due to the large leakage power for highly reliable design of high-performance systems. In this paper, an analytical methodology for estimating the junction temperature and initial temperature range was provided to avoid diverging junction temperature status in nano-scale devices. For this purpose, junction temperature decision (JTD) map and initial temperature limit (ITL) map was newly introduced.

Thermal Characterization of Multi Stack Packages Using Linear Superposition Method

As the mobile products have been developed, many devices of various functions should be packaged into the limited space. Therefore, stacking multi-packages is needed for small form factor. Compared with discrete packages, multi stack packages (MSP) can provide better solutions for power saving, EMI reduction, max frequency up-grade in spite of its higher cost, low test yield, poor quality assurance, and more complicated manufacturing process. But, stacking many packages in confined space has raised concerns related to heat dissipation, which has become one of the most serious problems in the design of MSP. Accordingly, a method to obtain Tj for each chip from the power inputs is needed. This is quite significant at the MSP promotion and design stage, though the temperature value would be changed by system environment. In this paper, a new approach to determine the junction temperatures of the MSP is proposed. The average temperature of the chips was calculated by RSM, and the temperature difference from the average temperature was calculated by linear superposition. Using this approach, one can calculate device junction temperatures simply and accurately

Micro cooling application on high density memory module

A numerical simulation and two kinds of experiments are conducted to investigate the thermal performance of several kinds of heat spreaders for high power memory modules. For numerical study, the commercial code, Flotherm, is used to model the 1GByte DDR memory module array. The convection heat transfer is analyzed for the memory module array with solid heat spreader under an airflow condition. For the wind runnel experiment, solid plate and block type spreaders are examined to obtain the thermal resistance of conjugate heat transfer of the solid under various airflow conditions. Also, to clarify the thermal characteristics and cooling capacity of liquid heat transport, newly designed liquid cooling devices, such as an embedded heat pipe spreader and vapor chamber with micro-wick structure are proposed and evaluated by the heat transport experiment with a water cold plate under the insulation condition.