Jörg Berthold

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated. Static measurements of single devices and dynamic measurements of ring oscillators and 32-b parallel prefix adders are presented. Whereas forward biasing still provides a significant performance improvement of up to 37% for low-leakage devices with 2.2-nm gate oxide thickness, the application of reverse biasing to reduce subthreshold leakage currents is inefficient due to additional leakage currents such as gate leakage and gate-induced drain leakage. Experimental results confirm that, in 90-nm CMOS circuits, the efficiency of body biasing strongly depends on the device type and operating temperature. Moreover, the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 /spl mu/m. Statistical threshold voltage variations are relevant for minimum-sized devices.

Sleep transistor circuits for fine-grained power switch-off with short power-down times

Fine-grained sleep transistor circuits are demonstrated with 0.12μm 16 b MAC (multiply-accumulate unit). Standby power is reduced by a factor of 5500 at 85°C with speed reduction of 5%. Charge recycling reduces the minimum sleep time by 25%. Dynamic power dissipation decreases by 16% activating a fraction of the switch in slow mode. Double switching inhibits power-on glitches and reduces current spikes by 38%.

Circuit design issues in multi-gate FET CMOS technologies

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

Architecture and implementation of a Software-Defined Radio baseband processor

The architecture and implementation of a Software Defined Radio (SDR) multi-standard baseband processor are presented. As the first representative of a new SDR baseband family, the X-GOLDTM SDR20 has been successfully designed and fabricated in a 65nm CMOS process. The physical layer signal processing for GSM, EDGE, GPRS, UMTS, HSPA, GMR1-3G, and LTE can be implemented in software on this single-chip device. Respective GSM, UMTS and LTE lab demonstrations have proven the competitiveness of this SDR approach.

Activation Technique for Sleep-Transistor Circuits for Reduced Power Supply Noise

Power gating is an effective leakage reduction technique with good scaling properties. The capability for a single cycle activation of large circuit blocks results as a consequence of sizing the sleep transistor for small delay degradation. However, in a system on chip environment this fast activation causes large current spikes and degrades the supply voltage of surrounding circuit blocks due to IR-drop and inductive voltage droop. To avoid timing errors in these blocks, a charge pump based activation technique is proposed and demonstrated experimentally. It is insensitive to process variations and can reduce the activation current to arbitrarily small values at the expense of an increased activation time. The capability for digital tuning allows for adaption of maximum activation current and latency to the system requirements. A monitor circuit tracks the virtual rail potential and indicates the end of the block activation

Efficiency of body biasing in 90 nm CMOS for low power digital circuits

This paper presents an evaluation of body biasing, based on measured static and dynamic device performance. The efficiency of body biasing in sub-130 nm CMOS circuits strongly depends on the device type and operating temperature. While forward biasing still provides a significant performance gain in a 90 nm CMOS triple well process, the efficiency of reverse biasing nearly vanishes. The impact of the zero temperature coefficient point on low voltage digital circuit design is investigated.

Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits

Energy dissipation, performance, and voltage scaling of Multi-Gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10 k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.

Influence of MOSFET geometry on the statistical distribution of NBTI induced parameter degradation

NBTI parameter degradation of MOSFETs shows a statistical variation. The distribution of the threshold voltage Vth after NBTI stress originates from a convolution of the distribution of the virgin devices together with the additional distribution of the NBTI degradation itself. The variability of the Vth (and other electrical parameters) of the virgin devices bases on process induced fluctuations of dopant atoms, oxide thickness, channel length, etc. The dependence on the transistor size is proven by several publications [e.g. 1,2]. The variability of the NBTI parameter degradation itself and the convolution is not fully understood yet and need further investigation. In this paper we investigate the dependency of the NBTI variability of Vth on the transistor size and geometry. For the necessary statistical relevance we perform NBTI stress experiments with the help of a smart array test-structure at a large amount of pMOS devices with various geometries. We show that the variability of pMOSFETs after NBTI depends not only on the size of the active area (w×l) but also on its geometry (w/l).