Stephan Henzler

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write operation. The trade-off for the use of independently controlled gates to increase the cell stability is discussed.

Power-Clock gating in adiabatic logic circuits

For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption caused by leakage currents, Power-Gating has been introduced. This paper presents for the first time Clock-Gating and Power-Gating in Adiabatic Logic. As the oscillator signal is both the power and the clock in Adiabatic Logic, a Power-Clock Gating is implemented using a switch to detach the adiabatic logic block from the oscillator. Depending on the technology the optimum switch topology and dimension is discussed. This paper shows that a boosted n-channel MOSFET as well as a transmission gate are good choices as a switch. Adiabatic losses are reduced greatly by shutting down idle adiabatic circuit blocks with Power-Clock Gating.

Time-to-Digital Converter Basics

On the basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representation in the voltage domain are discussed for nanometer CMOS technologies. Therewith, the advantages of a signal representation in the time domain are emphasized. The primary approach to time-to-digital converters (analog TDCs) based on a two step approach translating the time interval into a voltage and this voltage into a digital value is explained. Analog impairments and resolution limitations are examined. Counter based time interval measurement and delay-line based TDCs (digital TDCs) are introduced and analyzed with respect to operating principle, basic implementation issues, and quantization error, i.e. resolution.

Design and technology of fine-grained sleep transistor circuits in ultra-deep sub-micron CMOS technologies

The reduction of leakage currents in deep sub-micron CMOS is a challenging design criterion. The block level sleep transistor scheme is an established strategy to suppress static power consumption in unused circuit blocks. Suspending small logic blocks for even very short time intervals is the next step to cope with continuously increasing leakage currents. A design methodology for the power switch is demonstrated for a 16 bit multiply accumulate unit. A straightforward strategy to determine the minimum power-down time is demonstrated. A charge recycling scheme reduces the minimum power-down time by reducing the switching overhead. A double switch scheme reduces the on-current during block activation significantly and enables a faster block activation.

Digitalization of mixed-signal functionality in nanometer technologies

Digitalization of mixed-signal functionality, digital enhancement, all digital approach, and digital assistance are buzzwords in modern RF, analog and mixed-signal design. Based on a review of pipeline analog-to-digital converters, digital phase locked loops, time-to-digital converters and ADCs based on time quantization the meaning, the ideas, and the strategy behind these words are analyzed and discussed.

Theory of TDC Operation

This chapter addresses theoretical aspects of time-to-digital converters. First the basic shape of a TDC input–output characteristic is explained. The quantization error that arises from the mapping of a continuous into a discrete signal domain is revisited. Linear and non-linear imperfections of a TDC, namely offset and gain error as well as differential and integral non-linearities, are explained. Dynamic performance figures are motivated on the basis of analog-to-digital converters. The difference between ADC and TDC measurement is discussed. The interrelation between the single tone experiment of ADCs and the single shot experiment for TDCs is derived. An effective number of bits is defined for TDCs based on a single shot measurement. Therewith, an ADC compliant figure of merit is defined for TDCs. Local (process) variations are a critical issue for high resolution time-to-digital converters. Variations hit TDCs in the buffer tree of the stop signal, the delay-line, and the comparators. The susceptibility of each of these components is analyzed individually. Finally, the particular variation effects are combined.

Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits

Quasi adiabatic circuits like the efficient charge recovery logic (ECRL) are known to reduce dynamic power dissipation of digital CMOS circuits significantly. The possible operation frequencies have been continuously increased due to technology scaling. Anyway, the field of operation is limited to medium performance applications. If it was possible to operate a given adiabatic circuit also at extremely high frequencies there would be many new applications: A circuit working at a medium frequency most of the time and at high frequencies only for some burst mode operations could be implemented in adiabatic logic. This paper presents a new perspective of adiabatic circuits called adiabatic mode circuits. These circuits can be operated in a quasi adiabatic low-power mode but also in a high frequency domino mode if high speed data processing is required. Based on the 3-transistor DRAM cell a novel 3-transistor memory cell capable for adiabatic and conventional operation is presented. Thus new systems with a small total power consumption but temporarily high performance can be constructed.

Time-to-Digital Converters with Sub-Gatedelay Resolution – The Third Generation

So far, the resolution of time-to-digital converters is limited by technology to one inverter delay. For higher resolution circuit techniques are required that do not depend on a single absolute gate delay. This chapter focuses on such techniques, i.e. on TDCs for sub-gate delay resolution. The main concepts are the TDC based on parallel scaled delay elements, the Vernier TDC, the pulseshrinking TDC, and the local passive interpolation TDC. All concepts are explained in detail and analyzed with respect to resolution, dynamic range, area, power, and variability. Special emphasis is given to the last point in order to estimate the maximum feasible and achievable resolution under manufacturability considerations: In principle all concepts mentioned above can achieve an arbitrarily high resolution. In practice, however, the resolution is limited by process variations. The gated ring oscillator based TDC is discussed as a TDC architecture that has the ability to achieve a high resolution by means of oversampling and noise shaping. Finally, the TDC based on time interval amplification is presented as a concept that does not scale the quantizer references but the measurement residue.

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes

Two different schemes to switch-off unused circuit blocks (ZigZag-cut-off scheme1 and n-/p-block MTCMOS cut-off scheme2,3,4,5,6 are examined in deep-submicron technologies by analytical investigation and simulation. The theoretical basis of the ZigZag-scheme is given and particular design constraints are discussed. It is shown that the power-saving benefits of the ZigZag-scheme are critically dependent on the gate-leakage, whereas n- or p-block switching keep their effectiveness. Finally it is derived that n-block switching tends to cause severe glitch activity during power-up process degrading both power-up-time and energy loss. The ZigZag-scheme however does not suffer from this effect. The advantages and drawbacks of the two schemes are compared depending on the available technology generation. Finally recent extensions to ZigZag are discussed.

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.