Jorge L. Tonfat

Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs

Radiation effects such as soft errors are the major threat to the reliability of SRAM-based FPGAs. This work analyzes the effectiveness in correcting soft errors of a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLR-scrubbing). This correction technique can be implemented in a coarse grain TMR design. The FLR-scrubbing technique was implemented on a mid-size Xilinx Virtex-5 FPGA device used as a case study. The FLR-scrubbing technique was tested under neutron radiation and fault injection. Implementation results demonstrated minimum area and energy consumption overhead when compared to other techniques. The time to repair the fault is also improved by using the Internal Configuration Access Port (ICAP). Neutron radiation test results demonstrated that the proposed technique is suitable for correcting accumulated SEUs and MBUs.

Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis HLS is a powerful method to explore different design architectures in FPGAs. In this paper, we analyze four different design architectures implemented in a 28i?źnm SRAM-based FPGA under fault injection to analyze the probability of errors of them. We compare the information of essential bits provided by Xilinx with the susceptible bits obtained by fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. There is a trade-off in the number of errors classified as silent data corruption and timeout errors according to the architecture and DSP blocks usage. The proposed characterization method can be used to guide designers to select the most efficient architecture concerning the susceptibility to upsets and performance efficiency.

Low power 3–2 and 4–2 adder compressors implemented using ASTRAN

This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper are combined optimizations at logic, electrical and physical level. At the logic level, the circuit is optimized by using multiplexers instead of XOR gates to reduce delay, power and area. At the electrical level, this work presents an architecture that generate the XOR and XNOR signals simultaneously, this reduce internal glitches hence dynamic power as well. And finally at the physical level, and automatic layout generation tool (ASTRAN) is used to make the adder compressors layouts. This tool has proved to reduce power consumption and delay due to the smaller input capacitances of the complex gates generated compared to manual-designed layouts.

Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors

The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.

Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs

Reliability is a major design constraint for critical applications. SRAM-based FPGAs are attractive to critical applications due to their high performance and flexibility. However, they are high susceptible to radiation effects such as soft errors. Memory scrubbing is an effective method to correct soft errors in SRAM memories but it imposes an overhead in terms of logic area and energy consumption. This work proposes a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLR-scrubbing) with minimum energy consumption overhead without compromising the correction capabilities. As a case study, the FLR-scrubbing controller was implemented on a mid-size Xilinx Virtex-5 FPGA device, occupying 8% of available slices and consumes six times less energy per scrubbed frame than a classic blind scrubber.

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based Field Programmable Gate Array (FPGA). Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical level for aging, soft error and different voltages in SRAM memory cells was described to investigate by simulation in more details the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.

Analyzing the Impact of Radiation-Induced Failures in Programmable SoCs

All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption and costs. Although modern commercial APSoCs offer a plethora of advantages, they are prone to experience Single Event Upsets. We investigate the impact of using different system architectures on an APSoC in the overall system failure rate. We consider different memory organization, different communication schemes, and different computing modes. Results show that there are several choices of architectures and resources to be chosen to implement an application in an APSoC, but there are logic resources that can increase or decrease the vulnerability of the entire system to failures in the application execution context.

SET susceptibility estimation of clock tree networks from layout extraction

Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments

SRAM-based FPGAs are attractive to many high reliable applications at ground level due to its high density and configurability. However, due to its high sensitivity to neutroninduced soft errors, the FPGA configuration memory bits may suffer unexpected bit-flips and consequently critical errors may occur. To cope with this problem, authors have proposed several mitigation techniques, which must be verified under the presence of faults. Since ground-level radiation experiments are very costly, fault injection is a suitable method to verify mitigation techniques in early stages of development. In this work, we present a fault injector platform implemented in a FPGA commercial board able to inject multiple bit-flips in the configuration memory bits of SRAM-based FPGAs based on a fault database collected on radiation experiments. We show the accuracy of our proposed fault injection campaign compared to radiation test results. We compare the soft error rate of three designs under the accumulation of multiple faults.