Eduardo Chielle

Evaluating Selective Redundancy in Data-Flow Software-Based Techniques

This paper presents an analysis of the efficiency of using selective redundancy applied to registers in software-based techniques. The proposed selective redundancy chooses a set of allocated registers to be duplicated in software in order to provide detection of upsets that occur in the processor hardware and provokes data-flow errors. The selective redundancy is implemented over miniMIPS microprocessor software. A fault injection campaign is performed by injecting single event effect upsets in the miniMIPS hardware. Results show error detection capability, performance degradation and program memory footprint for many case studies. With that, designers can find the best trade-off in using selective redundancy in software.

Configurable tool to protect processors against SEE by software-based detection techniques

This paper presents a tool capable of automatically adding fault detection capabilities in software to protect the processors against transient faults. The tool implements a set of configurable software-based detection techniques over the assembly code of an unprotected program. The developed tool has been validated for two distinct processors: MIPS and LEON3. But it can be extended to other architectures and organizations by changing the configuration files. A fault injection campaign was performed and simulation results show high detection rates to both processors and a small increase in area and runtime.

S-SETA: Selective Software-Only Error-Detection Technique Using Assertions

Software-based techniques offer several advantages to increase the reliability of processor-based systems at very low cost, but they cause performance degradation and an increase of the code size. To meet constraints in performance and memory, we propose SETA, a new control-flow software-only technique that uses assertions to detect errors affecting the program flow. SETA is an independent technique, but it was conceived to work together with previously proposed data-flow techniques that aim at reducing performance and memory overheads. Thus, SETA is combined with such data-flow techniques and submitted to a fault injection campaign. Simulation and neutron induced SEE tests show high fault coverage at performance and memory overheads inferior to the state-of-the-art.

Evaluating the effectiveness of a diversity TMR scheme under neutrons

This paper explores the concept of Design Diversity Redundancy (DDR) applied to SRAM-based FPGAs as a proposal to increase system reliability. Three different implementations of an 8×8 matrix multiplication associated to majority voters were used to build a Diversity Triple Modular Redundancy (DTMR) scheme. The whole architecture was prototyped on a Xilinx Virtex5 FPGA and exposed to a neutron source for approximately 21 hours in order to investigate the occurrence of Single Event Effects. In addition, a fault injection campaign was performed in order to compare simulation and experimental data. Results indicate the ability of the system to tolerate faults.

Analyzing the Impact of Radiation-Induced Failures in Programmable SoCs

All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption and costs. Although modern commercial APSoCs offer a plethora of advantages, they are prone to experience Single Event Upsets. We investigate the impact of using different system architectures on an APSoC in the overall system failure rate. We consider different memory organization, different communication schemes, and different computing modes. Results show that there are several choices of architectures and resources to be chosen to implement an application in an APSoC, but there are logic resources that can increase or decrease the vulnerability of the entire system to failures in the application execution context.

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

Designing and analyzing a SpaceWire router IP for soft errors detection

SpaceWire (SpW) is a well know communication standard platform proposed by European Space Agency (ESA). Due to its inherent properties of fault-tolerant and high-throughput, it is extensively used in avionics and satellite applications. When more than two SpW nodes communicate, a SpW Router is used. Such routers can be implemented in ASICs or in programmable devices. In order to perform fault tolerance experiments and since was not possible to find an open source of SpW Router, in this paper we present an open VHDL implementation of this router. Simulation was performed in order to validate the system, and synthesis results for ASIC and FPGA are presented. Finally, in order to analyze the SpW router behavioral when soft errors happen, a fault injection campaign was implemented and results were presented.

Analyzing the Failure Impact of Using Hard- and Soft-Cores in All Programmable SoC under Neutron-Induced Upsets

We investigate the impact of using different system architectures on an APSoC, such as memory organization, communication schemes and by using hard- and soft-cores in the same context, in the final system failure rate.

Soft-Error Probability Due to SET in Clock Tree Networks

Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.

Overhead Reduction in Data-Flow Software-Based Fault Tolerance Techniques

There is an increasing interest in aerospace industry to increment the flexibility of the systems and reduce their cost. In this way, FPGAs offer several advantages as low-cost platform to deploy customized systems. However, the use of sub-micron technologies has increased their sensitivity to radiation-induced transient faults. Therefore, the mitigation of soft errors in systems based on soft-core microprocessors has become a major concern not only in the case of configuration memory protection, but also in the case of data and control-flow maintenance. Software-based fault tolerance techniques represent a valid alternative to improve the reliability in such systems at a reduced cost, but the associated time and memory overheads can limit their applicability. This chapter provides different implementation alternatives of software-based techniques in order to reduce overheads while keeping the reliability at the same level.