Lucas A. Tambara

Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

In this paper, we propose a method that combines dedicated test designs, readback and bitstream comparisons to investigate soft errors in a nanoscale SRAM-based FPGA under photoelectric stimulation. Static test is performed to analyze the SEU dependency to voltage supply. Static cross-section and threshold energy are presented. Dynamic test is accomplished by using a set of designs in order to diagnose errors from SET in the logic clock tree, SEU in embedded soft-core processor and in the reconfigurable ICAP interface. A picosecond laser is used in the experiments.

Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis HLS is a powerful method to explore different design architectures in FPGAs. In this paper, we analyze four different design architectures implemented in a 28i?źnm SRAM-based FPGA under fault injection to analyze the probability of errors of them. We compare the information of essential bits provided by Xilinx with the susceptible bits obtained by fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. There is a trade-off in the number of errors classified as silent data corruption and timeout errors according to the architecture and DSP blocks usage. The proposed characterization method can be used to guide designers to select the most efficient architecture concerning the susceptibility to upsets and performance efficiency.

S-SETA: Selective Software-Only Error-Detection Technique Using Assertions

Software-based techniques offer several advantages to increase the reliability of processor-based systems at very low cost, but they cause performance degradation and an increase of the code size. To meet constraints in performance and memory, we propose SETA, a new control-flow software-only technique that uses assertions to detect errors affecting the program flow. SETA is an independent technique, but it was conceived to work together with previously proposed data-flow techniques that aim at reducing performance and memory overheads. Thus, SETA is combined with such data-flow techniques and submitted to a fault injection campaign. Simulation and neutron induced SEE tests show high fault coverage at performance and memory overheads inferior to the state-of-the-art.

Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors

The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.

Heavy Ions Induced Single Event Upsets Testing of the 28 nm Xilinx Zynq-7000 All Programmable SoC

The recent advance of silicon technology has allowed the integration of complex systems in a single chip. Nowadays, Field Programmable Gate Array (FPGA) devices are composed not only of the programmable fabric but also by hard-core processors, dedicated processing block interfaces to various peripherals, on-chip bus structures and analog blocks. Among the latest released devices of this type, this work focuses in the 28 nm Xilinx Zynq-7000 All Programmable SoC (APSoC). While not immune to the radiation environment in space, the Zynq-7000 seems to be very attractive for the aerospace sector due to its high computational power capability and low-power consumption. In this work, results from heavy ions testing for Zynq-7000 are presented. The experiments were performed in a Brazilian facility located at the University of São Paulo, Brazil.

Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC

This paper describes a neutron-induced single event effect test in analog-to-digital converters of a Microsemis programmable commercial mixed-signal system-on-chip. The main objective is to investigate the reliability of the charge redistribution successive approximation register architecture of the analog-to-digital converters (SAR-ADC) embedded into this device, considering critical application projects. The case-study circuit is a data acquisition system that uses the two available analog-to-digital converters (ADCs), being one converter controlled by the embedded processor and the other by the digital programmable matrix of the device. This scheme is based on a design diversity redundancy concept. The setup was exposed to a neutron source at the CCLRC Rutherford Appleton Laboratory - ISIS in order to investigate the occurrence of SEEs ranging from single to errors bursts. Also, SPICE simulations were carried out in a charge redistribution SAR-ADC architecture in order to clarify the results obtained from this experiment.

Evaluating the effectiveness of a diversity TMR scheme under neutrons

This paper explores the concept of Design Diversity Redundancy (DDR) applied to SRAM-based FPGAs as a proposal to increase system reliability. Three different implementations of an 8×8 matrix multiplication associated to majority voters were used to build a Diversity Triple Modular Redundancy (DTMR) scheme. The whole architecture was prototyped on a Xilinx Virtex5 FPGA and exposed to a neutron source for approximately 21 hours in order to investigate the occurrence of Single Event Effects. In addition, a fault injection campaign was performed in order to compare simulation and experimental data. Results indicate the ability of the system to tolerate faults.

Analyzing the Impact of Radiation-Induced Failures in Programmable SoCs

All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption and costs. Although modern commercial APSoCs offer a plethora of advantages, they are prone to experience Single Event Upsets. We investigate the impact of using different system architectures on an APSoC in the overall system failure rate. We consider different memory organization, different communication schemes, and different computing modes. Results show that there are several choices of architectures and resources to be chosen to implement an application in an APSoC, but there are logic resources that can increase or decrease the vulnerability of the entire system to failures in the application execution context.

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments

SRAM-based FPGAs are attractive to many high reliable applications at ground level due to its high density and configurability. However, due to its high sensitivity to neutroninduced soft errors, the FPGA configuration memory bits may suffer unexpected bit-flips and consequently critical errors may occur. To cope with this problem, authors have proposed several mitigation techniques, which must be verified under the presence of faults. Since ground-level radiation experiments are very costly, fault injection is a suitable method to verify mitigation techniques in early stages of development. In this work, we present a fault injector platform implemented in a FPGA commercial board able to inject multiple bit-flips in the configuration memory bits of SRAM-based FPGAs based on a fault database collected on radiation experiments. We show the accuracy of our proposed fault injection campaign compared to radiation test results. We compare the soft error rate of three designs under the accumulation of multiple faults.