José Manuel Cazeaux

Modeling Crosstalk Effects in CNT Bus Architectures

Carbon nanotubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, issues associated with crosstalk among bus lines implemented by CNTs are investigated in detail. CNT-based interconnects are modeled and the effects of crosstalk on performance and correct operation are evaluated by simulation. Existing models are modified to account for geometries in bus architectures made of parallel single-walled nanotubes and a single multiwalled nanotube. New RLC equivalent circuits are proposed for these bus architectures. A novel bus architecture with low crosstalk features is also proposed. This bus architecture is made of dual-walled nanotubes arranged in parallel. In this architecture, the crosstalk-induced delay and corresponding uncertainty (as well as crosstalk-induced peak voltage) are significantly reduced; a modest area penalty is incurred. Reductions up to 59% for the crosstalk-induced delay and up to 81% for the crosstalk-induced peak voltage are reported. These results confirm that the proposed bus arrangement noticeably improves performance and provides reliable operation

Accurate Linear Model for SET Critical Charge Estimation

In this paper, we present an accurate linear model for estimating the minimum amount of collected charge due to an energetic particle striking a combinational circuit node that may give rise to a SET with an amplitude larger than the noise margin of the subsequent gates. This charge value will be referred to as SET critical charge (QSET). Our proposed model allows to calculate the QSET of a node as a function of the size of the transistors of the gate driving the node and the fan-out gate(s), with no need for time costly electrical level simulations. This makes our approach suitable to be integrated into a design automation tool for circuit radiation hardening. The proposed model features 96% average accuracy compared to electrical level simulations performed by HSPICE. Additionally, it highlights that Q SET has a much stronger dependence on the strength of the gate driving the node, than on the node total capacitance. This property could be considered by robust design techniques in order to improve their effectiveness.

New high speed CMOS self-checking voter

Faults possibly affecting voters of TMR (triple modular redundancy) systems, employed in high reliability applications, can make them provide the fan-out logic with incorrect data, hence making the adoption of the TMR technique useless. In this paper we instantiate the need for self-checking voters and we propose a new self-checking voting scheme that, compared to alternate self-checking solutions, features the advantage of being faster, while requiring comparable power consumption. This is achieved at the cost of a small increase in area overhead.

The other side of the timing equation: a result of clock faults

We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven by Metra et al. (2004). Therefore, new testing/DFT approaches are needed to avoid the dramatic impact of clock faults on product quality and operation in the field. Various possible approaches are discussed.

Self-Checking Voter for High Speed TMR Systems

In this paper we address the problem of faults possibly affecting voters of TMR systems and making them provide incorrect majority data, thus making the adoption of the TMR technique useless. We consequently instantiate the need for self-checking voting schemes and propose a new CMOS self-checking voter that, compared to alternate self-checking solutions, features the advantage of being faster, while requiring comparable power consumption and a small increase in area overhead.

Low-area on-chip circuit for jitter measurement in a phase-locked loop

In this paper we propose a novel on-chip circuit to measure the jitter present at the output of phase-locked-loops (PLLs) used for synthesizing a clock with equal or higher frequency than the input clock. This measure is performed at every period of the PLL reference clock. The obtained digital outputs are encoded by means of a thermometer code. Our proposed circuit is able to measure the jitter of PLLs, providing an output frequency in the GHz range. Compared to other available techniques, that proposed here requires lower cost in terms of area overhead (implying an increase in PLL area <4%) and circuit complexity, while featuring comparable accuracy and test time.

Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects

In this paper we present a novel circuit for the on-line detection of transient and crosstalk faults affecting the interconnects of systems implemented using field programmable gate-arrays (FPGAs). The proposed detector features self-checking ability with respect to faults possibly affecting itself thus being suitable for systems with high reliability requirements, like those for space applications. Compared to alternate solutions, the proposed circuit requires a significantly lower area overhead, while implying a comparable, or lower, impact on system performance. We have verified our circuit operation and self-checking ability by means of post-layout simulations

Clock Faults Induced Min and Max Delay Violations

In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.

A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features

Carbon Nano Tubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep sub-micron (silicon-based) technologies due to their robustness to electromigration. In this paper, a novel bus architecture with low crosstalk features is proposed. It is made of dual-walled nanotubes (DWNTs) arranged in parallel. It achieves reductions up to 72% of the crosstalk-induced delay, and up to 76% for the crosstalk-induced peak voltage, at a modest area increase. Therefore, the proposed bus arrangement significantly improves performance and provides reliable operation in an interconnect.