Martin Omana

Latch Susceptibility to Transient Faults and New Hardening Approach

In this paper, we analyze the conditions making transient faults (TFs) affecting the nodes of conventional latch structures generate output soft errors (SEs). We investigate the susceptibility to TFs of all latch nodes and identify the most critical one(s). We show that, for standard latches using back-to-back inverters for their positive feedback, the internal nodes within their feedback path are the most critical. Such nodes will be hereafter referred to as internal feedback nodes. Based on this analysis, we first propose a low-cost hardened latch that, compared to alternative hardened solutions, is able to completely filter out TFs affecting its internal feedback nodes while presenting a lower susceptibility to TFs on the other internal nodes. This is achieved at the cost of a reduced robustness to TFs affecting the output node. To overcome this possible limitation (especially for systems for high-reliability applications), we propose another version of our latch that, at the cost of a small area and power consumption increase compared to our first solution, also improves the robustness of the output node, which can be higher than that of alternative hardened solutions. Additionally, both proposed latches present a comparable or higher robustness of the input node than alternative solutions and provide a lower or comparable power-delay product and area overhead than classical implementations and alternative hardened solutions.

A model for transient fault propagation in combinatorial logic

Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.

Multiple transient faults in logic: an issue for next generation ICs?

In this paper, we first evaluate whether or not a multiple transient fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the same word, but not both). By means of electrical level simulations, we show that this can be the case. Then, we present a software tool that we have developed in order to evaluate the likelihood of occurrence of such bidirectional errors for very deep submicron (VDSM) ICs. The application of this tool to benchmark circuits has proven that such a probability can not be neglected for several benchmark circuits. Finally, we evaluate the behavior of conventional self-checking circuits (generally designed accounting only for single TFs) with respect to such events. We show that the modifications generally introduced to their functional blocks in order to avoid output bidirectional errors due to single TFs (as required when an AUED code is implemented) can significantly reduce (up to the 40%) also the probability to have bidirectional errors because of multiple TFs.

Novel transient fault hardened static latch

University of Bologna

Low Cost NBTI Degradation Detection and Masking Approaches

Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming a great concern for current and future CMOS technology. In this paper, we propose two monitoring and masking approaches that detect late transitions due to NBTI degradation in the combinational part of critical data paths and guarantee the correctness of the provided output data by adapting the clock frequency. Compared to recently proposed alternative solutions, one of our approaches (denoted as Low Area and Power (LAP) approach) requires lower area overhead and lower, or comparable, power consumption, while exhibiting the same impact on system performance, while the other proposed approach (denoted as High Performance (HP) approach) allows us to reduce the impact on system performance, at the cost of some increase in area and power consumption.

Accurate Linear Model for SET Critical Charge Estimation

In this paper, we present an accurate linear model for estimating the minimum amount of collected charge due to an energetic particle striking a combinational circuit node that may give rise to a SET with an amplitude larger than the noise margin of the subsequent gates. This charge value will be referred to as SET critical charge (QSET). Our proposed model allows to calculate the QSET of a node as a function of the size of the transistors of the gate driving the node and the fan-out gate(s), with no need for time costly electrical level simulations. This makes our approach suitable to be integrated into a design automation tool for circuit radiation hardening. The proposed model features 96% average accuracy compared to electrical level simulations performed by HSPICE. Additionally, it highlights that Q SET has a much stronger dependence on the strength of the gate driving the node, than on the node total capacitance. This property could be considered by robust design techniques in order to improve their effectiveness.

Low cost scheme for on-line clock skew compensation

In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clocks routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and systems reliability.

Self-checking monitor for NBTI due degradation

Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming of great concern for current and future CMOS technology. In this paper we propose a monitor able to detect NBTI due late transitions in the combinational part of a critical data-path. It requires lower area than recently proposed alternative solutions, and a lower or comparable power consumption. Moreover, differently from alternative solutions, our monitor is also self-checking with respect to its possible internal faults, thus avoiding the useless negative impact on system performance and the negative impact on system reliability which could otherwise take place in case of non self-checking sensors, should they get affected by faults.

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic

We propose an on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of error detecting codes), we propose to look for the information redundancy (referred to as function-inherent codes) that the microprocessor control logic may inherently have, due to its required functionality. We will show that this allows to achieve on-line testing at significant savings in terms of area and power consumption, and with lower or comparable impact on system performance and design costs, compared to alternate, traditional on-line testing approaches.

Fast and low-cost clock deskew buffer

We propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution network or those due to power supply noise. Compensation/correction is performed instantaneously, during system run-time, upon skew occurrence. Compared to alternative solutions which can be used to compensate/correct skews between couples of clocks, that presented here is definitely faster, features lower area overhead and power consumption, and does not require any initialization phase at the beginning of system operation. Additionally, our proposed buffer is also able to compensate/correct clock duty cycle variations due to process parameter variations, as well as faults affecting the clock distribution network. Also in this case, compensation/correction is accomplished within the same clock cycle of duty-cycle variation occurrence.