Josep Maria Margarit

A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications

Mid-wavelength infrared (MWIR) thermography is an emerging technology with promising applications such as industrial monitoring, medicine and automotive, but its use in high-speed cameras is not yet widespread due to the lack of inexpensive sensor integration solutions and their common reliance on bulky cooling mechanisms. This work fills the gap by presenting a monolithic uncooled high-speed imager based on vapor-phase deposition lead selenide (VPD PbSe) photoconductors and a fully digital and configurable CMOS read-out integrated circuit (ROIC) to operate the MWIR imager. This ROIC features cancellation of PbSe dark current, compensation of its output capacitance and correction of the fixed pattern noise (FPN) caused by process non-uniformities in CMOS fabrication and detector deposition. The low-cost 80 × 80 imager has been integrated using 0.35 μm 2P4M standard CMOS technology and PbSe detector post-processing with 135 μm pixel pitch and 68% fill factor values. Experimental opto-electrical performance exhibits 10 bit real-time FPN compensation and DR calibration over the entire focal plane operating at 2 kfps, sub-0.5 LSB inter-pixel crosstalk, sub-μW pixel power consumption, and an overall figure of merit of 55 mK × ms.

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This paper presents a very low-power and fully programmable CMOS digital active pixel sensor for uncooled IR fast imaging. The proposed circuit topology includes self-biasing, built-in input capacitance compensation, predictive A/D conversion, and a truly digital I/O interface, all at pixel level. Furthermore, full fixed pattern noise cancellation is also supplied by the external digital tuning of both offset and gain for each individual pixel at no speed costs. Two DPS circuit implementations for IR PbSe sensors have been integrated in standard 0.35-mum 2-polySi 4-metal CMOS technology. Finally, exhaustive experimental results from their electrical tests are reported to validate the proposed DPS design techniques.

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This paper presents a new low-power and compact digital active pixel sensor (APS) for hybrid CMOS imagers. The proposed self-biased topology includes built-in dark current and input capacitance compensation, mixed integration, A/D conversion and a purely digital I/O interface, all at pixel level. Furthermore, full FPN compensation and AGC capabilities are also supplied by digitally pre-programming the individual sensitivity of each APS during the read-out phase without any speed reduction. In this sense, experimental results are reported for a 100mumtimes100mum complete APS circuit in standard 0.35mum CMOS 2-polySi 4-metal technology for IR applications.

Fully Tunable CMOS DPS for Uncooled Infrared Fast Imaging

This paper presents a novel digital pixel architecture for MWIR PbSe sensors and high-speed AER imagers. Low-power and compact circuits are proposed for pixel built-in log-domain temporal contrast, signal adapted self-biasing, linear current to spike frequency conversion under high-speed AER communications, and digital PLL-based technology and temperature compensated tuning. The proposed CMOS design techniques make extensive use of transistor subthreshold operation and circuit reuse. The resulting 40µm-pitch digital pixel is designed in standard 0.35µm 2P4M CMOS technology, and preliminary simulation results are reported.

A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers

This paper presents a new CMOS active pixel sensor specifically for digital X-ray imagers. The proposed DPS architecture includes a novel lossless A/D conversion scheme, a dark current self-cancellation mechanism, as well as self-biasing and built-in test capabilities, all at pixel level. Furthermore, FPN compensation is achieved by introducing gain programmability inside the A/D converter of each individual pixel. The proposed CMOS circuits make extensive use of subthreshold transistor operation and circuit reuse to obtain a low-power and compact DPS cell. A circuit implementation in standard 0.18 μm CMOS 1-polySi 6-metal technology is presented together with experimental preliminary results.

A self-biased PLL-tuned AER pixel for high-speed infrared imagers

This paper presents a new low-power and fully programmable digital CMOS active pixel sensor for uncooled and fast IR imagers. The proposed self-biased topology includes built-in input capacitance compensation, mixed integration, A/D conversion and a purely digital I/O interface, all at pixel level. Furthermore, full FPN compensation is also supplied by digital tuning of the individual offset and gain of each DPS during read-out at no speed costs. Two circuit implementations for IR PbSe sensors have been integrated in standard 0.35 mum CMOS 2-polySi 4-metal technology, and exhaustive experimental data is presented from electrical tests.

A 0.18µm CMOS low-power charge-integration DPS for X-ray imaging

This paper presents a complete family of integrate- and-fire modulator (IAF) topologies to improve in-pixel signal linearity in digital imagers. Three types of soft-reset schemes are analyzed for capacitive trans-impedance amplifiers (CTIAs). The proposed Type III has the main advantages of avoiding any low-impedance voltage source or extra capacitor, of including correlated double sampling (CDS) for the cancellation of CTIA low-frequency noise, and of minimum current biasing requirements. Comparative electrical simulations are also presented to demonstrate the linearity improvements of soft-reset schemes and the increase of IAF modulation robustness under low-power circuit operation.

A Sub-μW fully programmable CMOS DPS for uncooled infrared fast imaging

This paper presents an integrated test platform for imagers, which allows their electrical characterization by directly injecting the input current in each individual pixel. The core of the proposed ITP is a matrix of controllable current sources featuring low technology dependence, together with easily scalable row and column DACs for the digital programming of every single pixel current. A 10 kfps 32×32 4 bit×4 bit ITP chip is integrated in a low-cost 2.5 μm 1M CMOS technology, reporting μA-range full-scale and background programmability and FPN levels below 5%rms. As a result, the proposed ITP achieves accurate stimulation of both image patterns and motion sequences with a compact test setup.

Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers

This work presents an architecture for CMOS active pixel sensors (APS) based on a novel lossless charge integration method, proposed for X-ray imagers in general but specifically optimized for full-field digital mammography. The objective is to provide all the required functionality inside the pixel, so to use full digital control and read-out signals only, therefore avoiding crosstalk between analog lines over large pixel arrays. It includes a novel lossless A/D conversion scheme besides a self-calibrating dark current cancellation circuit, a self-biasing circuitry, biphasic current sensing for the collection of electrons (e-) or holes (h+) and built-in test. Furthermore, FPN compensation is available by individually addressing the pixels internal DAC controlling the gain. Implemented in a 0.18μm 1P6M CMOS technology with MiM capacitors, everything fits into a 70μm by 70μm due to the extensive reuse of available blocks and aggressive layout techniques. Also, thanks to the MOSFET subthreshold operation, the average power consumption is as low as 8μW/pixel.