Josep Rius

Proportional BIC sensor for current testing

A new design of a BIC sensor for current testing static CMOS circuits is proposed. It is based on a lateral BJT device which is easy to incorporate in any standard CMOS process. The design diverts a fraction of the IDDQ current from the cell under test and a resistive component generates a voltage proportional to IDDQ. Additional features are the possibility of continuous measure of idd and increased speed of this sensor compared with sensors based on the current integration principle. The design does not have substrate currents due to the parasitic vertical BJTs. Experimental work on the sensor is reported.

IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption

A compact IR-drop model for on-chip power distribution networks in array and wire-bonded ICs is analyzed. Chip dimensions, size, and location of the supply pads, metal coverage, piecewise distribution of IC consumption, and the resistance between the pads and the power supply are considered to obtain closed-form expressions for the IR-drop. The IR-drop model is validated by comparing its results with electrical simulations. The obtained error is in the range of 1%.

A high-frequency nonquasi-static analytical model including gate leakage effects for on-chip decoupling capacitors

This paper presents a compact model for on-chip decoupling capacitors (decaps) including gate-oxide leakage. The model makes use of only four parameters, namely, channel resistance, gate-oxide capacitance, and two parameters to quantify gate-oxide leakage, to predict the static and dynamic response of decaps. Quality indices have been defined to enable development of decap design guidelines and evaluation of performance of such capacitors. The model shows how the gate leakage and longer channel lengths severely affect the performance of on-chip decaps for both low and high frequencies. The model also shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. Application of the model uncovers tradeoffs for thin- and thick-oxide capacitors in an available 90-nm CMOS technology. For a general-purpose technology, a reference capacitance value has been realized using decaps with a discrete width and length. Our model predicts that thick-oxide n-channel (p-channel) capacitors require /spl sim/3.37x (/spl sim/3.31x) more silicon area and /spl sim/1.70x (/spl sim/1.17x) degraded time response as compared to their thin-oxide versions. The time response is even more degraded (/spl prop/L/sup 2/) when longer channel decaps are used. This paper contributes by defining performance benchmarks for decaps.

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations and measurements. For 65 nm LP-CMOS, a close correlation has been obtained over a large frequency range from 10 MHz up to 10 GHz. Furthermore, we introduce the maximum decap admittance as a new metric for decap performance qualification. Closed-form expressions have been derived to calculate maximum admittance. Finally, we determine the relationship between relevant figure-of-merit parameters for decap design optimization.

Analysis of the extra delay on interconnects caused by resistive opens and shorts

The paper presents an analytical solution for the delay introduced by opens and shorts on RC interconnects. Starting from the set of PDEs that defines the dynamics of such lines, complete solutions are found. Compact expressions for the delay, derived from the complete solutions, show an excellent agreement when compared with simulations, for realistic values of interconnect parameters, driver resistance and an arbitrary values and place of the defect. This information is useful for testing of such interconnects.

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results

This paper compares a set of measurements of power consumption of CMOS circuits obtained from conventional and non-conventional measurement methods. A description of the advantages and disadvantages of each method is included as well as the precaution measures to prevent measurement errors. Experiments on a 32-bit microprocessor and a standard cell custom circuit prove that by using non-conventional methods it is possible to obtain information unreachable with conventional ammeter measurements.

Dynamic characterization of built-in current sensors based on PN junctions: analysis and experiments

The goal of this work is to analyze the performance of PN junction-based Built-in Current Sensors (BICS) for IDDQ testing. Two types of BIC Sensors are analyzed: one based on a simple PN junction as the sensing element (DBICS), and the other based on a lateral BJT (PBICS). The sensitivity, speed and performance of the BICS are studied by showing their dependence on circuit parameters. Design constraints of such sensors in order to achieve performance criteria on CUT and BICS are analyzed. The dynamic analysis of the BICS is compared with experimental results when the PN junction BICS are used on a CMOS circuit.

Detecting I/sub DDQ/ defective CMOS circuits by depowering

When disconnecting the power supply line of a CMOS circuit in its quiescent state, the capacitances present in the circuit hold the logic valves in all their nodes. In non defective circuits, these capacitances discharge very slowly due to the extremely small I/sub DDQ/ discharge current. On the other hand, in I/sub DDQ/ defective circuits the discharge is faster than in the previous case because the current involved is many orders of magnitude greater. Some time after the discharge starts, the logic state of some nodes may change, and when this change propagates to a primary output, the defect is detected. Experimental work has been performed to prove these effects and to evaluate their fault detection capabilities.

Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors

An RLC model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method to perform such calculation allows optimizing relevant PDN design parameters, such as number, size, and location of supply/ground pads and location of interblock decoupling capacitors, and width and pitch of metal tracks. The PDN model and impedance calculations are validated by comparing their results with SPICE simulations, giving a maximum error of less than 1%.An RLC model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method to perform such calculation allows optimizing relevant PDN design parameters, such as number, size, and location of supply/ground pads and location of interblock decoupling capacitors, and width and pitch of metal tracks. The PDN model and impedance calculations are validated by comparing their results with SPICE simulations, giving a maximum error of less than 1%.

An activity monitor for power/performance tuning of CMOS digital circuits

The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.