Salvador Manich

Fault-secure parity prediction arithmetic operators

Although parity prediction arithmetic operators are compatible with systems checked by parity codes, they are not secure against single faults. The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions.

Low power BIST by filtering non-detecting vectors

In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based on the fact that as the test progresses, the detection efficiency of the pseudo-random vectors decreases very quickly. Many of the pseudo-random vectors will not detect faults in spite of consuming a significant amount of energy from the power supply. In order to prevent this energy consumption, a filtering of the non-detecting vectors and a reseeding strategy are proposed.These techniques are evaluated on the set of ISCAS-85 benchmark circuits. Extensive simulations have been made using the SAIL energy simulator showing that, in large circuits, the energy consumption and the average power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy.

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

A methodology to find the couple of vectors maximizing the weighted switching activity in combinational CMOS circuits under variable delay model is presented. The weighted switching activity maximization problem is shown to be equivalent to a fault testing problem on a transformed circuit. A maximum weighted switching activity is achieved by test vectors covering a selected set of faults of the transformed circuit. Automatic Test and Pattern Generation tools are used to find the maximizing pair of vectors. The validity of the proposal is demonstrated on the ISCAS-85 benchmark circuits and the results show that the simulation time is reduced by an order of magnitude and the estimation of the maximum weighted switching activity is improved in comparison with pseudo-random sample simulation.

Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources

Test-pattern generators (TPGs), based on arithmetic operations, are becoming cost-effective built-in self-test solutions for circuits with embedded processors. Similar to pseudorandom TPGs, arithmetic TPGs use reseeding to reach high levels of fault coverage (FC). In this paper, we propose a method of searching for an effective reseeding strategy, guaranteeing a specified FC level. The proposed methodology minimizes the total test time under the constraint of the total memory resource allocated to store the seeds. The minimization is performed by a binary search that speeds up the seed selection. Experiments with benchmark circuits have shown an average reduction of 43.47% in test time compared with the three previous methodologies.

Detection of probing attempts in secure ICs

Physical attacks focus on extracting information from internal parts of ICs. One way to achieve this is by means of connecting probes to wires, so that the content of internal buses and registers can be revealed. Protection against this type of attacks exists, but usually is bulky and expensive, e.g. the shielding of secured areas. This paper presents a novel in-circuit countermeasure that is cheap and can easily be integrated in existing designs to detect probing attempts. It is based on a ring oscillator that operates over coupled lines in a differential mode. When the loading of one of the lines is unbalanced over a tolerance margin, an impulse is generated and integrated over time. If the integration surpasses a given threshold an alarm signal is activated. Simulations show the stability of the detector over a range of temperature and supply voltage variations.

Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementations

Parity prediction arithmetic operator schemes have the advantage that they are compatible with data paths and memory systems checked by parity codes. Nevertheless, the basic drawback of these schemes is that they may not be fault secure for single faults, since they propagate multiple output errors that are undetectable by the parity code. In this paper we derive necessary and sufficient conditions for parity prediction arithmetic operators to achieve the fault secure property. From these conditions, various fault secure designs for arithmetic operators are reported.

Improving security in cache memory by power efficient scrambling technique

The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead.

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results

This paper compares a set of measurements of power consumption of CMOS circuits obtained from conventional and non-conventional measurement methods. A description of the advantages and disadvantages of each method is included as well as the precaution measures to prevent measurement errors. Experiments on a 32-bit microprocessor and a standard cell custom circuit prove that by using non-conventional methods it is possible to obtain information unreachable with conventional ammeter measurements.

RRAM based cell for hardware security applications

Resistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs will poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write opeation of two paralled cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF)like primitive is implemented based on modified 1 transistor - 1 resistor (1T1R) array structure.

Defeating Simple Power Analysis attacks in cache memories

A wide range of attacks that target cache memories in secure systems have been reported in the last half decade. Cold-boot attacks can be thwarted through the recently proposed Interleaved Scrambling Technique (IST). However, side channel attacks like the Simple Power Analysis (SPA) can still circumvent this protection. Error detection and correction codes (EDC/ECC) are employed in memories to increase reliability, but they can also be used to increase the security. This paper proposes to boost the IST with an ECC code in order to create a cache resistant against SPA-attacks. The redundancy provided by the ECC code is used to create confusion by enlarging the search space where the hacker has to look for to find the secret keys.