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Dive into the research topics where Joseph M. Steigerwald is active.

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Featured researches published by Joseph M. Steigerwald.


Archive | 1997

Chemical Mechanical Planarization of Microelectronic Materials

Joseph M. Steigerwald; S. P. Murarka; Ronald J. Gutmann

Historical perspective CMP: variables and manipulations electrochemical and mechanical concepts for CMP processes copper CMP CMP of other materials post CMP cleaning.


Materials Chemistry and Physics | 1995

Chemical processes in the chemical mechanical polishing of copper

Joseph M. Steigerwald; S. P. Murarka; Ronald J. Gutmann; David J. Duquette

The mechanisms by which removal and planarization occur during the chemical mechanical polishing (CMP) of copper, used for pattern delineation in a multilevel metallization scheme, are investigated in this paper. We propose that removal occurs as mechanical abrasion of the surface followed by chemical dissolution of the abraded species. Planarization is achieved by the use of a rigid polishing pad that provides mechanical abrasion only to the high areas on the copper surface and by the formation of a surface layer on the copper during polishing to prevent dissolution of copper in the low areas. Fundamentals of electrochemistry are used to explain and predict both the dissolution of copper and the formation of a surface layer in the CMP slurry. Examples of polishing slurries are presented to demonstrate our hypotheses, including a complexing agent (ammonia) plus oxidizer (ferricyanide ion or nitrate ion) slurry and an oxidizing acid (nitric acid) plus corrosion inhibitor (benzotriazole) slurry. Finally, the mechanisms used to explain the CMP of copper are used to explain anomalous behavior during the CMP of titanium, in which the presence of copper ions in the polish slurry accelerates the polish rate of titanium. Titanium is used as a diffusion barrier and adhesion promoter for copper.


IEEE Electron Device Letters | 1994

Contact and via structures with copper interconnects fabricated using dual Damascene technology

S. Lakshminarayanan; Joseph M. Steigerwald; David T. Price; M. Bourgeois; T.P. Chow; Ronald J. Gutmann; S. P. Murarka

A novel submicron process sequence was developed for the fabrication of CoSi/sub 2//n/sup +/-Si, CoSi/sub 2//p/sup +/-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO/sub 2/ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O/sub 2/ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10/sup -6//spl Omega/-cm/sup 2/ or less. A specific contact resistivity value of 1.5/spl times/10/sup -8//spl Omega/-cm/sup 2/ was measured for metal/metal contacts.<<ETX>>


Thin Solid Films | 1995

Chemical-mechanical polishing of copper with oxide and polymer interlevel dielectrics

Ronald J. Gutmann; Joseph M. Steigerwald; Lu You; David T. Price; Jan M. Neirynck; David J. Duquette; S. P. Murarka

Chemical-mechanical polishing (CMP) of copper with oxide interlevel dielectrics has been demonstrated as a viable patterning approach for copper interconnect structures. This paper summarizes our understanding of the mechanisms involved in copper CMP and presents our results with both oxide interlevel dielectrics (ILDs) and low dielectric constant polymer ILDs. Our two-step model of copper CMP consists of mechanical abrasion of the copper surface followed by removal of the abraded material from the vicinity of the surface and has been developed after extensive electrochemical and CMP experiments with alternative slurries. Although the softer and less process tolerant polymers result in Damascene patterning difficulties compared with oxide ILDs, our results with both benzocyclobutene and parylene indicate that manufacturable processes for on-chip interconnect structures can be established with additional fundamental understanding and further development.


Thin Solid Films | 1995

Integration of copper multilevel interconnects with oxide and polymer interlevel dielectrics

Ronald J. Gutmann; T. Paul Chow; S. Lakshminarayanan; David T. Price; Joseph M. Steigerwald; Lu You; S. P. Murarka

Copper interconnect structures are being evaluated for 0.25 μm minimum feature size technology and below. This work focuses on fabrication of one- and two-level test structures with copper metallization and both oxide and polymer interlevel dielectrics to demonstrate the compatibility of unit processes being developed for future copper-based interconnects. Emphasis is placed on dual Damascene patterning and material and process compatibility with such patterning and the required barriers and passivation techniques required with copper. Future directions of this work are described in this invited review paper.


MRS Proceedings | 1994

Surface Layer Formation During the Chemical Mechanical Polishing of Copper Thin Films

Joseph M. Steigerwald; S. P. Murarka; David J. Duquette; Ronald J. Gutmann

Three chemical processes that occur during the chemical mechanical polishing (CMP) of copper are described in terms of their effect on surface planarity, polish rate, and corrosion resistance of the polished copper. These processes are surface layer formation, dissolution of mechanically abraded copper, and chemical acceleration of the polish rate. The role of these processes is demonstrated with two slurry formulations used in the CMP of copper at Rensselaer.


Journal of Electronic Materials | 1996

Electrochemical effects in the chemical-mechanical polishing of copper for integrated circuits

C. A. Sainio; David J. Duquette; Joseph M. Steigerwald; S. P. Murarka

Chemical-mechanical polishing of copper in ammonia based solutions has been studied using electrochemical techniques such as electrochemical potential, linear polarization resistance, and potentiodynamic polarization. A copper rotating disk electrode was used to simulate polishing conditions. Measurements made on sputter-coated wafers during polishing were used for comparison. The dissolution of copper is limited by transport of Cu(NH3)2+ from the surface, and the removal rate of copper during polishing is controlled in the solution by the formation of copper ammine complexes.


biennial university government industry microelectronics symposium | 1995

An investigation of the chemical mechanical polishing of copper thin films to form in-laid interconnections in the dielectric (SiO/sub 2/) films

Joseph M. Steigerwald; S. P. Murarka; Ronald J. Gutmann; David J. Duquette

Summary form only given. Describes an investigation of the chemical mechanical polishing (CMP) of copper films for the purpose of delineating and planarizing inlaid copper interconnections for multilevel metallization in silicon integrated circuits. Copper CMP has been shown to be an effective method of patterning interconnections and for providing the global planarity required to build multilevel structures. CMP processes in general, however, remain poorly understood and unoptimized. The task of optimizing a process is hampered by the lack of a fundamental understanding of the removal mechanisms at work in CMP. A fundamental understanding of these mechanisms will allow greater control of the CMP process in the manufacturing environment.


Archive | 1995

Systems for performing chemical mechanical planarization and process for conducting same

S. P. Murarka; Ronald J. Gutmann; David J. Duquette; Joseph M. Steigerwald


Chemical Mechanical Planarization of Microelectronic Materials | 2007

Chemical Mechanical Planarization—An Introduction

Joseph M. Steigerwald; S. P. Murarka; Ronald J. Gutmann

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Ronald J. Gutmann

Rensselaer Polytechnic Institute

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S. P. Murarka

Rensselaer Polytechnic Institute

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David J. Duquette

Rensselaer Polytechnic Institute

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David T. Price

Rensselaer Polytechnic Institute

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Lu You

Rensselaer Polytechnic Institute

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S. Lakshminarayanan

Rensselaer Polytechnic Institute

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C. A. Sainio

Rensselaer Polytechnic Institute

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Jan M. Neirynck

Rensselaer Polytechnic Institute

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M. Bourgeois

Rensselaer Polytechnic Institute

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T. Paul Chow

Rensselaer Polytechnic Institute

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