Joseph N. Y. Aziz

256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes

A 3D microsystem for multi-site penetrating extracellular neural recording from the brain is presented. A 16 times 16-channel neural recording interface integrated prototype fabricated in 0.35 mum CMOS occupies 3.5 mm times 4.5 mm area. Each recording channel dissipates 15 muW of power with input-referred noise of 7 muVrms over 5 kHz bandwidth. A switched-capacitor delta read-out data compression circuit trades recording accuracy for the output data rate. An array of 1.5 mm platinum-coated microelectrodes is bonded directly onto the die. Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology.

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplication. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is performed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise accumulation during ADC readout. A 128 times 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35 mum standard CMOS technology. The 4.4 mm times 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.

Brain–Silicon Interface for High-Resolution in vitro Neural Recording

A 256-channel integrated interface for simultaneous recording of distributed neural activity from acute brain slices is presented. An array of 16 times 16 Au recording electrodes are fabricated directly on the die. Each channel implements differential voltage acquisition, amplification and band-pass filtering. In-channel analog memory stores an electronic image of neural activity. A 3 mm times 4.5 mm integrated prototype fabricated in a 0.35-mum CMOS technology is experimentally validated in single-channel extracellular in vitro recordings from the hippocampus of mice and in multichannel simultaneous recordings in a controlled environment

256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes

A 16times16-channel 3.5times4.5mm2 neural recording interface is fabricated in 0.35mum CMOS and is integrated with on-chip 3D Au and Pt microelectrodes. Each channel dissipates 15muW with an input-referred noise of 7muV over 5kHz bandwidth. A switched-capacitor delta read-out data-compression circuit trades recording accuracy for the output data rate. In-vitro experimental results validate the circuit design and the on-chip 3D electrode bonding technology

Real-time seizure monitoring and spectral analysis microsystem

We present a neural recording and spectral analysis integrated microsystem. It is the instrumentational and computational core of an envisioned miniature implantable brain implant for automated epileptic seizure therapy. The microsystem combines two functional blocks: the neural recording interface and the spectral analysis processor. The neural interface contains 256 signal acquisition channels recording neural field potentials from an array of 16 times 16 electrodes simultaneously, in a distributed fashion. The spectral analysis processor computes a wavelet-based time-frequency map (spectrogram) of the neural recording. We demonstrate the functionality of the integrated microsystem in real-time epileptic seizure monitoring and spectral analysis, as necessary for subsequent automated seizure prediction and prevention

In Vitro Epileptic Seizure Prediction Microsystem

The architecture and VLSI implementation of an epileptic seizure prediction microsystem are presented. The microsystem comprises a neural recording interface and a seizure prediction processor. The two functional blocks have been prototyped in a 0.35 mum CMOS technology and experimentally characterized. The integrated microsystem is validated in predicting the onsets of seizures off line in an in vitro epilepsy model of recurrent spontaneous seizures in the hippocampus of mice.

Towards Real-Time In-Implant Epileptic Seizure Prediction

We present an architecture of an epileptic seizure prediction system suitable for an implantable implementation. The microsystem comprises a neural interface, a spectral analysis processor and an artificial neural network (ANN). The neural interface and the spectral analysis processor have been prototyped in a 0.35 mum CMOS technology with experimental results are presented. The wavelet-based artificial neural network predicts the onsets of seizure up to two minutes before their occurrence in an in-vitro epilepsy model using a mouse hippocampal brain slice with recurrent spontaneous seizures

CMOS image compression sensor with algorithmically-multiplying ADCs

A 128×128 CMOS image compression sensor fabricated in a 0.35µm CMOS process is reported. It computes block-matrix and convolutional image transforms with digital kernels of up to 8×8 pixels directly on the focal plane. A pixel output is sampled only when the corresponding bit of the kernel coefficient is one. Bit-wise accumulation of adjacent pixel outputs in a column is performed by the switched-capacitor accumulator circuit. A column-parallel algorithmic multiplying ADC performs binary-weighted summation by adding the accumulator circuit outputs with cyclic residues of the same binary weight. The signal range is maintained by generating two bits per cycle. The imager performs three computations per pixel readout. Image compression experimental results at 30fps and 8-bit output resolution are presented.

256-channel integrated neural interface and spatio-temporal signal processor

We present an architecture and VLSI implementation of a distributed neural interface and spatio-temporal signal processor. The integrated neural interface records neural activity simultaneously on 256 voltage-mode channels. Each channel implements differential signal acquisition, amplification and band-pass filtering. An array of in-channel double-memory sample-and-hold cells stores two 16 times 16 electronic images of distributed neural activity consecutively in time. A column-parallel double sampling circuit performs frame differencing in order to identify spatio-temporal neural activity patterns. A 3 mm times 4.5 mm integrated prototype was fabricated in a 0.35 mum CMOS technology. The functionality of the neural interface was experimentally demonstrated in extracellular in vitro recordings from the hippocampus of mice. The utility of the on-sensory-plane signal processor was validated in simulated wavefront detection performed on experimentally measured distributed neural activity recording

Electro-chemical multi-channel integrated neural interface technologies

We present a comparative review of two multichannel integrated neural interface technologies. The first integrated neural interface prototype performs simultaneous current-mode acquisition of 16 independent channels of redox currents ranging five orders of magnitude in dynamic range over four scales down to hundreds of picoamperes. The second neural interface acquires neural field potentials in microvolts to millivolts range on a 16times16-electrode microarray in voltage mode. Each microsystem features programmable gain amplifiers, tunable band filters, configurable sample-and-hold circuits, and is ready for external analog-to-digital conversion. The current-mode and voltage-mode neural interface prototypes have been experimentally validated in chemical and electrical neural activity monitoring respectively. Side-by-side quantitative comparison of the two neural interface technologies is given