Vadim Smolyakov

VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-Best MIMO detector

This paper presents a VLSI architecture of a novel soft-output K-Best MIMO detector. The proposed detector attains low computational complexity using three improvement ideas: relevant discarded paths selection, last stage on-demand expansion, and relaxed LLR computation. A deeply pipelined architecture for a soft-output MIMO detector is implemented for a 4×4 64-QAM MIMO system realizing a peak throughput of 655Mbps, while consuming 174K gates and 195mW in 0.13um CMOS. Synthesis results in 65nm CMOS show the potential to support a sustained throughput up to 2Gbps achieving the data rates envisioned by emerging IEEE 802.16m and LTE-Advanced wireless standards.

Continuous-Time Digital Signal Processing Based Controller for High-Frequency DC-DC Converters

This paper introduces a digital dual-mode controller for low-power high-frequency dc-dc switch-mode power supplies (SMPS) suitable for on-chip implementation. In steady state the controller behaves as a conventional digital PWM controller, and during transients it utilizes continuous-time digital signal processing to achieve very fast transient response. The continuous time DSP is triggered by a sudden change of output voltage. Then it performs a charge-balance based algorithm to achieve voltage recovery through a single on-off action of the power switch. The effectiveness of the method is demonstrated on an experimental 5 V-to- 2V, 400 kHz, 2.5 W buck converter that recovers voltage in the time equivalent to 3 PWM switching cycles, approaching converter physical limitations.

Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture

A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

A phase synchronization and magnitude processor VLSI architecture for adaptive neural stimulation

A low-power VLSI processor architecture that computes in real time the magnitude, phase and phase synchronization of two input signals is presented. The processor is part of an envisioned closed-loop implantable or wearable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized in a standard 1.2V 0.13μm CMOS technology utilizes 41,000 logic gates. For 64 input channels, it dissipates 1.1μ W per input, and provides 1kS/s per-channel throughput when clocked at 1.41MHz. The power scales linearly with the number of input channels or the sampling rate.

VLSI multivariate phase synchronization epileptic seizure detector

A low-power VLSI seizure detector is presented. It combines a 256-channel analog neural recording chip and a low-power synthesized digital VLSI processor. The processor computes the bivariate phase synchronization on any two neural inputs from a set of 256 and their instantaneous magnitude. For experimentation with in vitro epilepsy models, a low-cost technique to implement on-chip gold microelectrodes was utilized. Results are shown using an in vitro low Mg2+ mouse epilepsy model and human EEG data.

Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems

The growing density of integration and the increasing percentage of system-on-chip area occupied by embedded memories has led to an increase in the expected number of memory faults. The soft memory repair strategy proposed in this paper employs existing forward error correction at the system level and mitigates the impact of memory faults through permutation of high-sensitivity regions. The effectiveness of the proposed repair technique is evaluated on a multi-megabit de-interleaver static random access memory of an ISDB-T digital baseband orthogonal frequency-division multiplexing receiver in 65-nm CMOS. The proposed technique introduces a single multiplexer delay overhead and a configurable area overhead of ⌈M/i⌉ bits, where M is the number of memory rows and i is an integer from 1 to M, inclusive. The repair strategy achieves a measured 0.15 dB gain improvement at 2×10-4 quasi-error-free bit error rate in the presence of stuck-at memory faults for an additive white Gaussian noise channel.

A WiMAX/LTE compliant FPGA implementation of a high-throughput low-complexity 4×4 64-QAM soft MIMO receiver

This paper presents a prototype of a high-throughput 4×4 64-QAM MIMO receiver consisting of a channel matrix QR decomposition, a soft-output K-Best MIMO detector and a Convolutional Turbo Code decoder. The proposed MIMO receiver provides low processing latency and a pipelined architecture scalable to a larger number of antennas and constellation order. Therefore, it is suitable for LTE-Advanced and IEEE 802.16m broadband wireless standards. A rapid prototyping platform interfacing MATLAB with Xilinx ISE was used in the development of the 4×4 64-QAM MIMO receiver. The receiver utilizes 96% of the slice LUTs and 78% of slice registers on Virtex-5 FX130T FPGA, operating at a maximum frequency of 125MHz.