Ju-hyuck Chung

PMOS body-tied FinFET (Omega MOSFET) characteristics

In this paper, we introduce PMOS body-tied FinFet characteristics. For this work, the 0.1/spl mu/m design ruled SRAM technology was used. I/sub D/-V/sub DS/ characteristics show that /spl Omega/ MOSFET apparently has lower DIBL characteristics than conventional PMOS transistor. On current of the /spl Omega/ MOSFET is higher than that of conventional device and can be improved by optimising unit processes.

Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory

Through the evaluation and analysis of the data retention characteristics, it was found that the CTF memory cell behaviors are quite different from conventional that of the FG type flash memory cell in terms of Arrhenius plot of data retention because Ea of the CTF memory cell has a high dependency on the bake temperature and P/E cycles. A proper acceleration test condition is needed to predict the data retention lifetime of the CTF memory, considering the change of Ea in the low temperature region (<125°C).

New effect of Ti-capping layer in Co salicide process promising for deep sub-quarter micron technology

A new effect of the titanium (Ti) capping layer on cobalt (Co) silicide formation, which is promising for salicidation applications in deep sub-quarter micron devices, was investigated. TEM, SIMS, and XRD data suggest that Ti on top of the cobalt layer diffuses into the Co/Si interface and dissociates the thin silicon oxide at the interface during RTA. As a result, with a Co/Ti process, the sensitivity of Co salicide processes to surface conditions could be minimized, which gives a larger process window to fabricate deep sub-quarter micron devices.