Jintaek Park

8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 /spl mu/m/sup 2/, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm 2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line

Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the trap layers between gate lines suggests that the lateral charge spreading via trap layers from the programmed cells to the adjacent erased cells contributes to the charge loss of the TANOS cells.

A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond

A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements

Self Aligned Trap-Shallow Trench Isolation Scheme for the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

In the proposed new scheme, which is named self aligned trap-shallow trench isolation (SAT-STI), such process damage on high-k layer can be minimized, achieving the goal of isolating the storage nitride layer successfully.

Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si)NAND Flash Memory with Rounded Corner (RC) Structure

Charge trap flash (CTF) memory is one of the most promising technologies for the next generation NAND technology. Among various CTF memories, excellent manufacturability of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) structure has been successfully developed by achieving 32Gb MLC NAND flash using 40nm technology node (Y. Park et al., 2006). 3 dimensional NAND cells such as hemispherical corner (HC) (D. Kwak et al., 2007) and FinFET TANOS (S. Lee et al., 2006) devices with suppressed short-channel effects and improved data retention characteristic were also proposed as cell structures for the next generation beyond 40nm technology node. However, understanding of other device characteristics such as disturb characteristics of the structures is still insufficient. In this paper, various device characteristics of rounded corner (RC) TANOS including disturb and data retention characteristics are investigated and compared with the conventional planar TANOS. Finally, the rendering of RC TANOS for improving disturb characteristics was proposed.

New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory

Through the evaluation and analysis of the data retention characteristics, it was found that the CTF memory cell behaviors are quite different from conventional that of the FG type flash memory cell in terms of Arrhenius plot of data retention because Ea of the CTF memory cell has a high dependency on the bake temperature and P/E cycles. A proper acceleration test condition is needed to predict the data retention lifetime of the CTF memory, considering the change of Ea in the low temperature region (<125°C).

Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V/sub th/ distribution of 0.6V fulfilling the MLC operation is obtained while maintaining fast programming speed and sufficient cell current.

Effective Atmospheric-Pressure Plasma Treatment toward High-Performance Solution-Processed Oxide Thin-Film Transistors

Solution-processed oxide semiconductors (OSs) have attracted much attention because they can simply, quickly, and cheaply produce transparent channels on flexible substrates. However, despite such advantages, in the fabrication process of OS thin-film transistors (TFTs) using the solution process, it is a fatal problem that there are hardly any ways to simply and effectively control important TFT parameters, including the turn-on voltage ( Von) and on/off current ratio. For the practical application of solution-processed OS TFT, approaches to simply and effectively control the parameters are urgently required. Here, we newly propose an atmospheric-pressure plasma (APP) treatment that can simply and effectively control the electrical properties in solution-processed InO x TFTs. Through exposure of APP, we successfully realized the changes in important TFT parameters of solution-processed InO x TFT, Von from -11.4 to -1.9 V and the on/off current ratio from ∼103 to ∼106, which still keep up the high field-effect mobility (>20 cm2 V-1 s-1). On the basis of various analyses such as X-ray-based analysis and UV-visible spectroscopy, we identified that the APP treatment can effectively control oxygen vacancy and carrier concentration in solution-processed OS.

A comprehensive study of degradation behavior of select transistors in the Charge Trap Flash memories

The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.