Il-Goo Kim

Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process

The primary candidate for the barrier/etch stop layer in damascene process is silicon nitride. However, silicon nitride has a high dielectric constant. To reduce the effective dielectric constant in the copper damascene structure, silicon carbide, which is prepared by plasma enhanced chemical vapor deposition (PECVD) using 3 methyl silane source (Z3MS), is studied for the dielectric copper diffusion barrier. The dielectric constant of PECVD α-SiC:H is varied from 4.0 to 7.0 and the fourier transform infrared (FTIR) spectra peak intensity ratio of Si–CH3 bond to Si–C is also examined. The reduction in dielectric constant of α-SiC:H using 3MS gas seems to be related to the decreased density upon incorporation of Si–CH3 groups. The value of capacitance with α-SiC is 8–10% lower than that with PECVD SiN. The leakage current with α-SiC:H barrier is lower by 1 order of magnitude than that with PECVD SiN barrier.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm Lgate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.

Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

Process integration of CVD Cu seed using ALD Ru glue layer for sub-65nm Cu interconnect

Chemical-vapor-deposited(CVD) Cu film was successfully demonstrated as a seed layer for Cu electroplating, by using atomic-layer-deposited(ALD) Ru as a glue layer on ALD WNC barrier metal. Low via resistance of below 3/spl Omega//via was obtained in 0.13 /spl mu/m via chains, which was built in SiOC (k=2.9) intermetal dielectric. The adhesion between WNC and CVD Cu. estimated by mELT, was significantly improved by the insertion of ALD Ru and HR-XTEM analysis showed no interfacial layers at both Cu/Ru and Ru/WNC interfaces. In addition, Ru was found to promote the 2-D planar growth of CVD Cu film rather than the 3-D island growth.

Effect of mechanical strength and residual stress of dielectric capping layer on electromigration performance in Cu/low-k interconnects

We present the effect of mechanical strength and residual stress of dielectric barrier on electromigration performance in Cu/low-k interconnects. It has been discovered that mechanical strength and residual stress of dielectric capping layer have a great role on EM performance. The use of mechanically strong dielectric capping material with high residual compressive stress in Cu/low-k interconnects improves a structural confinement of Cu line. Also, it helps tensile stress level decrease near via bottom and compressive stress level increase at Cu beneath SiCN along Cu line. Reduction of tensile stress at via bottom would effectively suppress void nucleation and growth. Moreover, increase of compressive stress in Cu beneath SiCN alleviates Cu migration through that pathway, leading to a longer lifetime of interconnect component.

Cost-effective "BARC/resist-via-fill free" integration technology for 0.13 /spl mu/m Cu/low-k

Demonstrates the first successful integration scheme free of BARC/resist via-fill that not only significantly simplifies the overall process complexity, but also reduces cost and process instabilities by employing an OSG (k=2.9)/ HDP-FSG dual ILD structure in conjunction with our proprietary plasma induced polymeric etch stopper (PIPS) in a 7-metal level 0. 13 /spl mu/m design node. The via poisoning problem and low selectivity of etch stopper were overcome by optimizing ILD structure and PIPS etch process. The electrical characteristics and reliability results indicate that the current integration scheme is highly manufacturable.