Jue-Hsien Chern

Multilevel metal capacitance models for CAD design synthesis systems

An empirical model for multilevel interconnect capacitance is presented. This is the first model that allows designers to compute capacitances of arbitrary complex metal geometries. Such flexibility is achieved by a novel strategy of constructing complex geometries from simple primitive cells. Agreement with accurate simulations and measurements is within 8% over an extensive range of dimensions.<<ETX>>

Self-heating effects in basic semiconductor structures

Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

Design for reliability: the major challenge for VLSI

Selected integrated circuit (IC) reliability issues are discussed within the context of the design-in reliability concept. The electrical reliability issues discussed are latchup, electrostatic discharge, hot carrier effects, thin dielectric breakdown, and electromigration. Examples of the environmental reliability issues discussed are alpha -particle induced soft errors, thermal stress, mechanical stress, and corrosion. >

SIERRA: a 3-D device simulator for reliability modeling

SIERRA is a 3-D general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under DC, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5* to 7* speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and DRAM (dynamic random-access memory) single-event-upset studies is described. >

IVB-6 alpha-particle-induced charge transfer between closely spaced memory cells

A detailed analysis of various mechanisms involved in α-particle-induced charge transfer between two trench-type DRAM cells is reported. An analytical model has been developed to describe the charge-transfer mechanisms. The charge-collection process consists of two phases. In the first phase, funneling is tile dominant mechanism, and the axial current is calculated based on the drift component. In the second phase, the structure behaves similarly to a bipolar transistor, and both the drift and diffusion components contribute to the charge transfer. A discussion of the dependence of the charge transfer on stored charge, cell separation, charge in the α-particle track, and the substrate doping concentration is presented.

A parallel block-diagonal preconditioned conjugate-gradient solution algorithm for circuit and device simulations

The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.<<ETX>>

Algorithms for transient three-dimensional mixed-level circuit and device simulation

Algorithms for transient mixed-level circuit and device simulation using a full two-carrier three-dimensional (3-D) device simulator SIERRA and the circuit simulator SPICE3 are presented. Circuit and device simulator coupling algorithms that are suited for two-dimensional mixed-level circuit and device simulation using direct solvers cannot be successfully employed when iterative solution techniques are used in 3-D device simulation. New algorithms to couple the circuit and 3-D device simulator have been developed and evaluated. The importance of 3-D mixed-level circuit and device simulation is demonstrated by applying it to single-event upset in CMOS SRAM cells. >

Electrothermal simulation tools for analysis and design of ESD protection devices (NMOSFET)

Two- and three-dimensional simulators have been developed to investigate the electrothermal operation of semiconductor devices and conditions for onset of thermally activated second breakdown. There are two distinct breakdown modes, one associated with a pn-junction and the other with a resistor, that can cause thermal breakdown in transistors. Simple structures have been studied for a better understanding of second breakdown. Simulations coupled with experimental results also allow the evaluation of failure thresholds of MOS devices under ESD stress conditions. It is noted that 2-D simulations are pessimistic in predicting the failure thresholds and should be used for a study of qualitative trends only.<<ETX>>

A system for semiconductor process specification

The SPEC system for capturing and managing semiconductor fabrication process information is discussed. The SPEC data model decomposes process specifications into equipment, step, process, and flow hierarchies. Mechanisms within an interactive graphical user interface provide a high degree of user control over the expression and organization of objects within each layered hierarchy and control the information in terms of collection, propagation to other layers, and the appearance of the data within specification folders using a what you see is what you get (WYSIWYG) folder builder. Implementation on a concurrent object-oriented database permits simultaneous use of the SPEC system by many users. >

PGS and PLUCGS-two new matrix solution techniques for general circuit simulation

Two techniques for general circuit simulation, an intelligent, partial Gauss-Seidel scheme (PGS) and a preconditioned conjugate-gradient scheme (PLUCGS), are described. Both techniques are robust and accurate for bipolar and MOS analog and digital circuits. PGS is a novel combination of direct solution, using LU factorization, and iterative solution, using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Solution speeds up to 6 times faster than direct methods have been demonstrated and higher grains are anticipated for larger circuits. The second method, PLUCGS, uses a partial LU factorization as a preconditioner; a vectorized implementation on a CONVEX C-240 computer is 5-7 times faster than the direct solution method with only one-fourth the memory requirements.<<ETX>>