A. Chatterjee

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V.<<ETX>>

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.

Shallow trench isolation for advanced ULSI CMOS technologies

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space. The trench bottom is rounded to minimize stress. (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area. (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 0.16 /spl mu/m wide trenches free of voids. Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions. Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage. (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback. (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance.

Transistor design issues in integrating analog functions with high performance digital CMOS

Pocket or halo designs used in high performance digital CMOS design can degrade analog device performance. A new understanding of this phenomenon is presented using device simulation. The effect of pocket implant parameters on the trade-off between digital and analog performance is studied experimentally. Experimental data showing the beneficial effects of eliminating the pocket selectively from the drain end on analog performance is also shown.

Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100 nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced by the metal gate. This allows the temperatures after metal gate definition to be limited to 450/spl deg/C. Compared to pure SiO/sub 2/, the nitrided oxides provide increased capacitance with less penalty in increased gate current. A saturation transconductance (g/sub m/) of 1000 mS/mm is obtained for L/sub gate/=70 nm and t/sub OX/=1.5 nm. Peak cutoff frequency (f/sub T/) of 120 GHz and a low minimum noise figure (NF/sub min/) of 0.5 dB with associated gain of 19 dB are obtained for t/sub OX/=2 nm and L/sub gate/=80 nm.

An accurate bipolar model for large signal transient and ac applications

It is shown that models employing only two ac parameters can be accurate, at best, to first order in frequency. A new small signal model is presented, and it is demonstrated by comparison with exact results that only three ac parameters are sufficient to maintain model accuracy at much higher frequencies than achieved by any previous model. (At and below the unity gain frequency, ωT, the maximum magnitude error is 2% and the maximum phase error is 1.1°.) Analytic expressions are given for the 3 parameters. The validity of the charge sharing scheme of Ref. 1 is established. A large signal model is presented which can be easily and efficiently incorporated into the existing SPICE Gummel-Poon model.

Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (/spl les/33 /spl Aring/) and with high temperature (>950/spl deg/C) S/D annealing for 0.13 /spl mu/m CMOS applications. Close to ideal C-V characteristics are obtained indicating good Si/SiO/sub 2/ interface quality and free from gate depletion. The gate sheet resistance is about 2 ohm//spl square/, nearly constant down to 0.05 /spl mu/m. Under fixed effective fields, the electron and hole mobility are comparable to or slightly better than those of poly gate devices. Compared to poly gate devices, the W/TiN on 33 /spl Aring/ pure oxide has inferior charge-to-breakdown (Q/sub bd/) distribution under substrate (+V/sub G/) injection. However, a remote-plasma nitrided oxide (RPNO) can greatly improve the +V/sub G/ Q/sub bd/ distribution for the W/TiN case. Short-channel W/TiN pMOS transistors are fabricated with excellent characteristics down to L/sub gate//spl ap/0.07 /spl mu/m. For nMOS under +V/sub G/ direct tunneling (DT) or Fowler-Nordheim (F-N) tunneling injection with S/D grounded, the W/TiN device has a higher substrate hole current density (J/sub p/) than n/sup +/ poly-gate device (by about an order magnitude larger). This higher J/sub p/ is believed due to the tunneling of valence-band electron and thus has no impact on the thin (t/sub ox//spl les/33 /spl Aring/) gate oxide reliability.

A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 /spl mu/m CMOS technologies and beyond

Shallow trench isolation schemes using a LOCOS edge to avoid sharp corner effects are applied to 0.25 /spl mu/m and 0.18 /spl mu/m technologies. Two variations are studied. In the first case (Case A) a mini-LOCOS is grown and deglazed prior to trench etch whereas in the second case (Case B) the deglaze is omitted. Excellent narrow width effect is demonstrated. The V/sub T/ increases by /spl les/50 mV when the transistor width is reduced from 10 /spl mu/m to 0.3 /spl mu/m. Minimum isolation space of 0.3 /spl mu/m and minimum n/sup +/-to-p/sup +/ space of 0.6 /spl mu/m across a well boundary are demonstrated. Diode leakages and oxide reliability are reasonable. Transistor subthreshold characteristics show no double hump for Case A, while for Case B some devices indicate presence of double hump when a substrate back bias is applied. Despite the mini-LOCOS formation the width reductions are /spl les/0.05 /spl mu/m and excellent drive currents of 660 /spl mu/A//spl mu/m (NMOS) and 290 /spl mu/A//spl mu/m (PMOS) are achieved corresponding to I/sub off/=1 nA//spl mu/m and V/sub cc/=1.8 V.

Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies

The dielectric material used to fill trenches in Shallow Trench Isolation (STI) of transistors, is key to device performance. This paper (a) evaluates the integration of currently available dielectric technologies and (b) designs an optimized process scheme for 0.25 /spl mu/m node and beyond. A detailed study of LPCVD TEOS, SACVD oxide, Hydrogen-Silsesquioxane SOG (HSQ) and ICP (Inductively Coupled) HDP (High Density Plasma) CVD oxide, for STI, is presented for the first time. A novel ICP HDP-CVD process scheme is shown to have the advantages of single step, low thermal budget and high throughput as well as provide good gap-fill, low HF etch rate, low moisture uptake, low shrinkage with annealing, low diode reverse leakage and isolation at 0.3 /spl mu/m spacing.

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A manufacturable shallow trench isolation (STI) technology using high density plasma (HDP) CVD oxide as trench filling material is reported for the first time, and compared to using sub-atmospheric CVD (SACVD) oxide as filling material. HDP filled STI has excellent immunity to double-hump, better gate oxide integrity and inverse narrow width effect, due to its lower deglaze rate and thus better corner protection compared to the SACVD case. The /spl Delta/Vt (between W=10 and 0.18 /spl mu/m) are 150 mV (NMOS). And 60 mV (PMOS) for the HDP case, and the transistor width reduction is /spl les/0.03 /spl mu/m for both cases. Trench wall passivation and a low sputtering component during deposition are necessary for HDP to achieve low diode edge leakage. 0.28 /spl mu/m intra-well isolation (or 0.46 /spl mu/m min. pitch), 0.6 /spl mu/m n/sup +/-to-p/sup +/ isolation, latch-up holding voltage of 2 V at 0.5 /spl mu/m n/sup +/-to-p/sup +/ spacing, together with outstanding CMOS transistor and inverter performance, have been achieved. These results are either comparable to or better than the best results reported to date. It is concluded that HDP trench filling oxide is a viable approach, while SACVD oxide is marginally acceptable, for the STI of 0.25/0.18 /spl mu/m CMOS.