Juergen Gramss

Multi-Shaped E-Beam Technology for Mask Writing

Photomask lithography for the 22nm technology node and beyond requires new approaches in equipment as well as mask design. Multi Shaped Beam technology (MSB) for photomask patterning using a matrix of small beamlets instead of just one shaped beam, is a very effective and evolutionary enhancement of the well established Variable Shaped Beam (VSB) technique. Its technical feasibility has been successfully demonstrated [2]. One advantage of MSB is the productivity gain over VSB with decreasing critical dimensions (CDs) and increasing levels of optical proximity correction (OPC) or for inverse lithography technology (ILT) and source mask optimization (SMO) solutions. This makes MSB an attractive alternative to VSB for photomask lithography at future technology nodes. The present paper describes in detail the working principles and advantages of MSB over VSB for photomask applications. MSB integrates the electron optical column, x/y stage and data path into an operational electron beam lithography system. Multi e-beam mask writer specific requirements concerning the computational lithography and their implementation are outlined here. Data preparation of aggressive OPC layouts, shot count reductions over VSB, data path architecture, write time simulation and several aspects of the exposure process sequence are also discussed. Analysis results of both the MSB processing and the write time of full 32nm and 22nm node critical layer mask layouts are presented as an example.

Electron beam direct write: shaped beam overcomes resolution concerns

In semiconductor industry time to market is one of the key success factors. Therefore fast prototyping and low-volume production will become extremely important for developing process technologies that are well ahead of the current technological level. Electron Beam Lithography has been launched for industrial use as a direct write technology for these types of applications. However, limited throughput rates and high tool complexity have been seen as the major concerns restricting the industrial use of this technology. Nowadays this begins to change. Variable Shaped Beam (VSB) writers have been established in Electron Beam Direct Write (EBDW) on Si or GaAs. In the paper semiconductor industry requirements to EBDW will be outlined. Behind this background the Vistec SB3050 lithography system will be reviewed. The achieved resolution enhancement of the VSB system down to the 22nm node exposure capability will be discussed in detail; application examples will be given. Combining EBDW in a Mix and Match technology with optical lithography is one way to utilize the high flexibility advantage of this technology and to overcome existing throughput concerns. However, to some extend a common Single Electron Beam Technology (SBT) will always be limited in throughput. Therefore Vistecs approach of a system that is based on the massive parallelisation of beams (MBT), which was initially pursued in a European Project, will also be discussed.

Data Preparation for EBDW

If electron beam technology is used for direct writing on Si wafers (synonym EBDW) there have to be taken into account a number of specific issues concerning the layout data preparation differing considerably from those of mask writing. This is especially true because EBDW enables the most advanced technology levels which are in general one or two nodes ahead of the mainstream optical lithography. Consequently we will have to face up to additional challenges, such like high resolution and the corresponding CD - control parameters. In order to achieve acceptable turn around times the shaped beam writers have proven to be the tool of choice. To demonstrate this behind a practical background we describe our experiences collected during 300mm wafer exposures with a SB351/3050 tool installed at the Fraunhofer Center Nanoelectronic Technology (CNT) in Dresden/Germany. Appropriate solutions are presented showing how to execute such procedures like layout fracturing and Proximity Effect Correction (PEC) of high-density layouts on a Linux computing cluster. The CD accuracy of lines being of particular interest in connection with sub 50 nm patterns being analyzed and a new model-based method allowing the reduction of the before mentioned effect is evaluated. In any case, whether it is about short or time-consuming exposures, a precise forecast of the total processing time of the wafer in the e-beam exposure tool is of great importance. Practical findings from the use of a simulation tool specifically developed for this purpose are discussed in this paper.

Application results achieved with LINUX cluster for data preparation

The ever growing layout complexity and escalating data volumes to be handled in high-end mask making processes using variable-shaped beam writers (VSB) require totally new computing and software solutions for data preparation. The high-performance, cost-effective LINUX Cluster is the ideal tool to manage these challenging tasks and, in addition, offers the advantage of being upgradable and expandable for meeting future lithography requirements. In this paper different computer configurations are analyzed. As a logical consequence the data conversion issue, including Proximity Effect Correction, of VSB e-beam systems and their specific data formats are also reflected in this investigation. Distributed and multi-threading computing is compared highlighting the advantages of the distributed approach.

MSB for ILT masks

Multi Shaped Beam (MSB) throughput simulation results have already been published in the past. An IC mask set of a 32nm node logic device was one of the applications that had been analyzed in more detail. In this paper we want to highlight results of shot count and write time evaluations done for Inverse Lithography Technology (ILT) masks targeting the 22nm technology node. The test pattern data we used for these practice-oriented analyses was designed by DNP / Japan and created by Luminescent Technologies, Inc. / USA. To achieve reliable evaluation results, the influence of different MSB configurations on shot count and mask write time has been taken into account and will be discussed here. Exposure results of pattern details are presented and compared with the fracturing result. The MSB engineering tool we used for our investigations covers such major components like an electron-optical column, a precision x/y stage and the MSB data path.

Data prep: the bottleneck of future applications?

There is no doubt that shaped beam systems have been well established in the mask write community since the introduction of the 130nm technology node. Moreover, they are successfully advancing to conquer also the wafer direct write market. To be able to handle today and in the near future the tremendous data volumes with their characteristic complexity as well as to make use of such indispensable methods like PEC and Fogging corrections, new, sophisticated solutions are necessary to master the challenging 45nm technology node. However, we are aware that the 45nm node presents only an intermediate step, because, according to the international roadmap, we soon will be confronted with the hardware and software requirements of the next, the 32nm technology node. In this context it becomes more and more important to consider potential showstoppers, in our case the data preparation process To investigate this complex subject a Linux cluster computer featuring 3.6GHz clock rate CPUs, and a software package supporting distributed computing with a 64Bit version and address units down to 0.1nm were used. The work was focused on the performance of pattern samples down to the 45nm node. Both mask and wafer data as well as NIL template manufacturing were considered, data prep times and CPU loads were analysed. Furthermore, the user-friendly Leica Interface for Data Preparations (LINDA) was applied. In addition, an outlook to future hardware/software configurations for mastering the challenges of the 32nm node will be given. The results presented in this paper prove that data preparation is not the bottleneck of current and future applications.

Pattern data processing using 1-nm address grid

In the past years the address grid for layout design, data preparation and exposure has been constantly reduced. Currently the ITRS Roadmap specifies 4nm Mask Design Grid for the 100nm technology node. The possibilities and challenges of pattern data processing for the new generation of Leicas Shaped Beam (SB) exposure tools, called SB350MW, are highlighted in this paper. In this context such issues like data volume, data processing time and fracture quality for the new 1nm pattern data format are discussed in detail.

Electron-beam lithography data preparation based on multithreading MGS/PROXECCO

This paper will highlight an enhanced MGS layout data post processor and the results of its industrial application. Besides the preparation of hierarchical GDS layout data, the processing of flat data has been drastically accelerated. The application of the Proximity Correction in conjunction with the OEM version of the PROXECCO was crowned with success for data preparation of mask sets featuring 0.25 micrometers /0.18 micrometers integration levels.

Mask-writing system architecture and toolkit approach for 1G DRAM and beyond

The continued device scaling in the semiconductor industry has resulted in an acceleration of the respective technology roadmaps worldwide, which in turn is reflected in the constant pull-in of the lithography roadmaps. From the lithography toolmaker point of view this situation had to be answered with a consistent integrated equipment development roadmap. The general toolkit philosophy of the Leica ZBA300 family of E- beam systems incorporates such features and results in a harmonization of the development and usage of e-beam tools over a wide range of device generations. The theoretical advantages of shaped beam systems over raster scan in terms of edge definition as well as in terms of writing times become especially obvious when advanced masks with the emerging reticle enhancements like OPC are taken into account. It is the successful application of such techniques that will make the production of reticles for the 0.18 micron generation and below a commercially feasible enterprise.

Large-glass reticle writer: exposure strategy and mask handling

The world semiconductor industry is currently preparing itself for the next evolutionary step in the ongoing development of the integrated circuit, characterized by the 0.18 micrometers technology. These circuits will invariably be produced using conventional optical lithography techniques, but based on advanced photomasks reticles, with the possible assistance of new lithography techniques such as phase shift and optical proximity correction. As such, these reticles will need to be built to very much tighter specifications, with more complex patterns, and at very much smaller geometries, then current technologies. To add to the already complex engineering task for the mask tool makers, the new SEMI reticle standard will introduce a 230 mm by 230 mm large and 9 mm thick quartz glass blank that will have a weight of above one kilogram. The production of these advanced masks is therefore identified as a key enabling technology which will stretch the capabilities of the manufacturing process, and its equipment, to the limit.