Johannes Kretz

20 nm tri-gate SONOS memory cells with multi-level operation

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.

Multi-level p+ tri-gate SONOS NAND string arrays

Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found

20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices

New device concepts have been introduced to overcome the problems of planar microelectronic devices. The FinFET, which is a variant of the double gate transistor concept, is a promising approach, requiring very fine lithography and etching processes. These steps have been implemented as process modules in a loop to standard production. An electron beam lithography system has been optimized for nano-patterning down to 20 nm with emphasis on feature size, overlay accuracy and automation. A four-step pattern transfer process with hard masks has also been developed using a high density plasma tool. Structures with steep side walls could be etched. The fin structures are imaged in TEM with direct and elemental mapping. The analysis of the side wall deposited during the etching process reveals that the etching is carbon free.

Detailed characterization of hydrogen silsesquioxane for e-beam applications in a dynamic random access memory pilot line environment

Hydrogen silsesquioxane (HSQ) has interesting applications as an electron-beam resist and hardmask. In this work, HSQ was investigated with regard to the postcoat delay, isofocal dose for an optimum process window, e -beam proximity effect correction, and the molecular structure in order to better understand the processing. Several independent methods were set up and applied to characterize the structuring of HSQ with e-beam including contrast measurements, basedose-over-critical-dimension tests, the isofocal dose method, the doughnut test, and Fourier transform infrared analysis. HSQ was coated on 300mm bare silicon wafers and exposed with a 50kV variable shaped e-beam writer in the dynamic random access memory pilot line environment of Qimonda Dresden and Fraunhofer CNT. The postcoat delay showed no significant influence on the exposure results. A dose difference between the basedose and the isofocal dose was observed, which indicates a working point in a suboptimal process window related to the poor co...

Process integration of 20 nm electron beam lithography and nanopatterning for ultimate MOSFET device fabrication

An electron beam microscope based lithography system has been used to fabricate transistors with very small active areas and gate lengths. Electron beam exposures are performed after scanning predefined marks arranged in the actual write field, followed by an automatic adjustment of the beam deflection parameters. A placement accuracy of better than 10 nm has been achieved. High resolution features down to 20 nm were obtained using the organic resist calixarene. The optimum resist parameters for different feature widths were evaluated experimentally in advance. Exposure energies were kept below 10 keV in order to minimize radiation damage, increase resist sensitivity and achieve optimum alignment mark contrasts. Nanoetching was performed by a mixture of bromine and chlorine chemistries after pattern transfer into a hard mask and complete resist removal. Lines of 50 nm were transferred into silicon with a selectivity to TEOS of in excess of 300:1.

MAGIC: a European program to push the insertion of maskless lithography

With the willingness of the semiconductor industry to push manufacturing costs down, the mask less lithography solution represents a promising option to deal with the cost and complexity concerns about the optical lithography solution. Though a real interest, the development of multi beam tools still remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the mask less technology. The aim of the program is to develop multi beam systems from MAPPER and IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper draws the present status of multi beam lithography and details the content and the objectives of the MAGIC project.

Scanning spreading resistance microscopy of fully depleted silicon-on-insulator devices

Scanning spreading resistance microscopy (SSRM) is an electrical characterization tool used for the measurement of the 2D carrier distribution in semiconductor devices. In this technique an atomic force microscope is used to measure the local resistance of a semiconductor sample, which is related to the doping concentration. SSRM was performed in fully depleted silicon-on-insulator (FD-SOI) devices and was able to satisfactorily resolve the different doping regions of the devices. In order to increase the spatial resolution the measurements were repeated on a new PMOS-SOI transistor with a gate length of 300 nm and with a bevel in the polishing step of ∼ 20°. The effective gate length of the device was measured and even the gate oxide, with a nominal thickness of only 3 nm, could be resolved. This brings SSRM closer to the metrology requirements of the International Technology Roadmap for Semiconductors (ITRS).

PML2: the maskless multibeam solution for the 22nm node and beyond

Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam solution for the 22 nm half-pitch node and beyond. PML2 is targeted on using hundreds of thousands of individually addressable electron-beams working in parallel, thereby pushing the potential throughput into the wafers per hour regime. With resolution potential of < 10 nm, PML2 is designed to meet the requirements of several upcoming tool generations.

High throughput maskless lithography: low voltage versus high voltage

The beam energy is a driving design parameter for electron beam lithography systems. To be able to compare the differences of low kV (5 kV) and high kV (100 kV) for a high-throughput system the limitations of both types of systems are evaluated. First the effect on the CD uniformity and throughput is analyzed. For any shot noise limited system the dose that is needed to obtain a required CD uniformity can be calculated. This dose depends on the total spot size and the efficiency of the electrons in the resist. For a smaller spot less dose is required than for a large spot. The current in a single beam is also determined by the spot size. A larger spot has more current. With these parameters an optimization of the required dose, spot size and single beam current can be made. It is found that although for high kV it is easier to create a small spot with a high current the low resist-exposure efficiency of the high-energy electrons limits the throughput, because the required dose is large. It is also found that for 10 wafers per hour multiple lenses or columns are required. For practical reasons (a high kV lens cannot be made as small as a low kV lens) there is a clear preference for the use of low energy in high-throughput systems. Another aspect that is crucial in the lithography process is the overlay. One of the main differences between high and low energy systems is the power that is dissipated in the wafer and the resulting error due to expansion. It is found that for both energies wafer heating is an issue, but for low kV there seem to be solutions, while for high kV the problem is 30 times bigger.

Evaluation of hybrid lithography and mix and match scenarios for electron beam direct write applications

An overview about process window evaluation and characteristic features of photoresists for e-beam/optical hybrid lithography as well as mix and match applications and implementation into new integration concepts is given. For that, several commercially available deep ultraviolet (DUV) (248nm), ArF (193nm), and e-beam resist samples from various suppliers were exposed at Qimonda’s dynamic random access memory pilot line environment using both e-beam and optical exposure. Due to the diverse, sometimes contradictory requirements and properties of the different material platforms (e.g., resolution, sensitivity, vacuum stability, etch resistance, etc.), a unique material for true hybrid lithography is difficult to find. At least the tested DUV resist is limited applicable for e-beam exposures putting up with low e-beam sensitivity.