Julie Guillan

Strains in BaTiO3 thin film deposited onto Pt-coated Si substrate

The ferroelectric-paraelectric phase transition was investigated in BaTiO3 100nm thick film deposited on platinized Si substrate by measuring the lattice parameters as a function of temperature and the hysteresis loop at room temperature. The transition from paraelectric to ferroelectric phase takes place at ∼420K (instead of 400K for unconstrained single crystals), whereas the film is under high tensile elastic in-plane strain (0.34%) and high inhomogeneous strain (0.69%) along the growth direction. Comparison of the experimental results with recent theoretical calculations suggests a monoclinic ferroelectric phase at room temperature, where interface “dead layer” plays a key role.

Optimisation of Surface Capacitance and Leakage Currents on Ion Beam Sputtered SrTiO3-Based MIM Capacitors for Above IC Technology

SrTiO3 (STO) deposition was performed by Ion Beam Sputtering on Pt/TiO2/SiO2/Si substrates. We showed that curing annealing after top electrode deposition is essential to achieve low leakage currents. A decrease of the leakage currents for thinner STO layers was observed, due to grain boundaries roughness increase with STO layer thickness as it was demonstrated by AFM experiments in the TUNA mode. Characteristics suitable for high density capacitors integrated in Above IC technology were achieved: a 20 nm-STO layer crystallized at 450°C and cured after top electrode deposition displays a surface capacitance of 36 nF/mm2, leakage currents of 10−7A/cm2 at 1 MV/cm and a breakdown voltage of 6 V.

Self Aligned Barrier Approach: Overview on Process, Module Integration and Interconnect Performance Improvement Challenges

Self aligned barriers approaches are widely investigated because they lead to a strong improvement of the Cu/barrier interface adhesion generally considered as the limiting factor for the electromigration performance of Cu interconnects capped with dielectric barriers. In this paper, several ways to perform self aligned barrier integration, using either Cu line surface treatments or selective deposition process on top of Cu lines and their basic performance are detailed. Achieved electrical and reliability performance are discussed in terms of process, integration feasibility and related issues, and architecture (stand-alone or bi-layered stack) since the self aligned barriers can be introduced at different levels of complexity depending on the performance targets and the applications foreseen

Above IC integrated SrTiO3 high K MIM capacitors

This paper describes realization and characterization of SrTiO3 (STO) high K MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors.

Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectrics interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.

Integration of multi-level self-aligned CoWP barrier compatible with high performance BEOL

A hybrid CoWP/SiCN Cu passivation was integrated in a three-metal-level interconnect stack at 65 nm technology node using a porous ULK material (K=2.5). 5 and 20 nm thick Pd-free CoWP electroless barriers were evaluated using a standard trench first hard mask architecture (TFHM) integration scheme, with PVD, ALD or punch-through Ta-based metallization processes. This study evidenced strong interaction between CoWP and etching chemistries, inducing feature size modification. Results evidenced the successful integration of an ultra-thin electroless barrier with slight process tuning, whereas thicker one still requires specific etch process development or integration scheme modification

Demonstration of TFHM scalability to 32 nm node BEOL interconnect and extendibility to ELK k ≤ 2.3 dielectric material

A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.