G. Imbert

Influence of electron-beam and ultraviolet treatments on low-k porous dielectrics

The down scaling of complementary metal oxide semiconductor transistors requires materials such as porous low-k dielectrics for advanced interconnects to reduce resistance-capacitance delay. After the deposition of the matrix and a sacrificial organic phase (porogen), postcuring treatments may be used to create porosity by evaporation of the porogen. In this paper, Auger electron spectroscopy is performed to simultaneously modify the material (e-beam cure) and measure the corresponding changes in structure and chemical composition. X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy measurements in attenuated total reflection mode confirm the Auger results. The porogen removal and matrix cross-linking result in the formation of a Si–O–Si network under e-beam or ultra violet cure. The possible degradation of these materials, even after cure, is mainly due the presence of Si–C bonds.

Electronic and chemical properties of the TaN/a-SiOC:H stack studied by photoelectron spectroscopy for advanced interconnects

Thin TaN metallic barriers are used to prevent copper diffusion into porous low-k dielectrics such as a-SiOC:H for advanced interconnects. We investigate the detailed electronic properties of the TaN/a-SiOC:H stack. Here we combine ultraviolet and x-ray photoelectron spectroscopy to measure the chemical composition and the whole band diagram of the TaN/a-SiOC:H stack. An original interpretation based on the image-force model used for internal photoemission is suggested to explain the electric field effect induced by negative bias of a-SiOC:H. This model is used to extrapolate the unbiased electron affinity of the dielectric. TaN work function, a-SiOCH band gap, valence band maximum and electron affinity of 4.6, 7.7, 4.0, and 3.8 eV are respectively obtained. Kelvin force microscopy and spectroscopic ellipsometry confirm TaN work function and a-SiOC:H band gap measurements, respectively. From the full band diagram of the TaN/a-SiOC:H stack, an interfacial barrier height of 0.8 eV is deduced.

Modification of porous ultra-low K dielectric by electron-beam curing.

The impact of electron irradiation on ultra-low K (ULK) porous dielectric material used in advanced interconnects is analyzed using spectroscopic and electrical characterizations. The e-beam irradiation modifies the chemical composition, the porosity and the optical indexes. The effects of e-beam curing on electrical properties and dielectric reliability are also evaluated.

45 nm Node Multi Level Interconnects with Porous SiOCH Dielectric k=2.5

A 45nm node BEOL integration scheme is presented with 140nm metal pitch at local and intermediate levels and 70nm via size. The dual damascene (DD) process is performed in a full porous low-k (k=2.5) at line and via level in order to meet RC performance requirements. Parametrical results show functional via chains and good line resistance and serpentine continuity at 45nm node dimensions. Copper resistivity and electromigration performances were investigated for line widths below 50 nm upon using ALD and PVD barriers

Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectrics interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.

Integration of multi-level self-aligned CoWP barrier compatible with high performance BEOL

A hybrid CoWP/SiCN Cu passivation was integrated in a three-metal-level interconnect stack at 65 nm technology node using a porous ULK material (K=2.5). 5 and 20 nm thick Pd-free CoWP electroless barriers were evaluated using a standard trench first hard mask architecture (TFHM) integration scheme, with PVD, ALD or punch-through Ta-based metallization processes. This study evidenced strong interaction between CoWP and etching chemistries, inducing feature size modification. Results evidenced the successful integration of an ultra-thin electroless barrier with slight process tuning, whereas thicker one still requires specific etch process development or integration scheme modification

Hydrogen accumulation as the origin of delamination at the a-carbon/SiO2 interface

This work reports the characterization of the interface amorphous carbon (a-C)/SiO2 by neutron and X-ray reflectometry. Neutrons have shown the existence of an intermediate layer (IL) between the a-C and the SiO2 layers that was not evidenced by XRR. This IL has been associated with the accumulation of H inside the SiO2 layer near the interface with the a-C. The characteristics of this layer, in particular, its H-concentration and thickness, seem to be correlated with the weakness of this interface. A plot of the molecular weight as a function of the mass density for the SiO2 and the IL layers graphically demonstrates the risk of delamination of each sample. The combination of NR and XRR is shown to be a powerful technique in the characterization of layers and interfaces used in the micro/nanoelectronics industry. The same approach can be extended to other interfaces of interest involving hydrogen.

Reliability failure modes in interconnects for the 45 nm technology node and beyond

This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45 nm node thanks to fine optimizations of Cu barriers, Cu filling, and ULK surface quality.

Demonstration of TFHM scalability to 32 nm node BEOL interconnect and extendibility to ELK k ≤ 2.3 dielectric material

A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.