Julien De Vos

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes

The vision of the Internet of Things with ambient intelligence calls for the deployment of up to a trillion connected wireless sensor nodes (WSNs). Minimizing the carbon footprint of each node is paramount from the sustainability perspective. In ultra-low-power applications, the life-cycle carbon footprint results from a complex balance between both embodied and use-phase energies [1]. The embodied energy arises mainly from CMOS chip manufacturing, and is essentially proportional to die area. Use-phase energy depends on both active and sleep-mode power, because of long stand-by periods in WSNs. In this paper, we present an ultra-low-power 25MHz microcontroller SoC that fully exploits the versatility of a 65nm CMOS process with a low-power/general-purpose (LP/GP) transistor mix (dual-core oxide) to obtain: i) 7μW/MHz active power consumption due to a 0.4V ultra-low-voltage (ULV) thin-core-oxide (GP) CPU supplied by a 78%-efficiency embedded DC/DC converter; ii) 0.66mm2 die area for low embodied energy due to a compact converter design and a dual-VDD architecture, enabling the use of the foundrys 1V high-density 6T SRAM bitcell; and, iii) 1.5μW sleep-mode power due to body-biased sleep transistors embedded into the converter and thick-core-oxide (LP) MOSFETs for retentive SRAM and always-on peripherals (AOP). Moreover, an on-chip adaptive voltage scaling (AVS) system controlling the converter ensures safe 25MHz operation at ULV for all PVT conditions. A multi-Vt clock tree is also proposed to achieve reliable timing closure with low-power SoC features. Finally, a glitch-masking instruction cache (I

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes

) is implemented to reduce the access power of the 1V program memory (PMEM).

Green SoCs for a sustainable Internet-of-Things

In the context of wireless sensor nodes for the Internet-of-Things, there is a need for low-power high-performance computing cores for video monitoring applications. In this paper we present a custom 50MHz 32-bit microcontroller running at 0.37V built on a 65nm LP/GP CMOS process. Part of an energy-harvesting SoC with on-chip CMOS imager, it features adaptive voltage scaling, low-power 1.55μW sleep mode, and a variable-width SIMD pipeline and multiply/divide unit, achieving 7.7μW/MHz overall.

A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters

The vision of the Internet-of-Things (IoT) calls for the deployment of trillions of wireless sensor nodes (WSNs) in our environment. A sustainable deployment of such a large number of electronic systems needs to be addressed with a Design-for-the-Environment approach. This requires minimizing 1) the embodied energy and carbon footprint of the WSN production, 2) the ecotoxicity of the WSN e-waste, and 3) the Internet traffic associated to the generated data. In this paper, we study how ultra-low-power yet high-performance systems-on-a-chip (SoCs) in nanometer CMOS technologies can contribute to these objectives by allowing compact batteryless WSNs with on-node data processing. We then review latest results achieved at the Université catholique de Louvain in the field of green SoC design for a massive yet sustainable deployment of the IoT.

Pushing Adaptive Voltage Scaling Fully On Chip

This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequency to maximize the converter efficiency. When the parasitic capacitances are low, this solution leads to an identical contribution of the switches and transfer capacitors to the converter output impedance. As the parasitic capacitances increase, the optimum switching frequency decreases. Secondly, optimum capacitor and switch sizes for maximum efficiency are provided. We show that the overdrive voltage strongly impacts the optimum switch width through the modification of their conductance. To support the sizing methodology, a model of the efficiency of switched-capacitor DC/DC converters is developed. It is validated against simulation and measurement results in 65 nm and 0.13 μm CMOS, respectively. The proposed sizing methodology shows how the converter efficiency can be traded-off for die area reduction and what is the impact of parasitic capacitances on the converter sizing.

Switched-capacitor DC/DC converters for empowering Internet-of-Things SoCs

In this paper, we investigate the possibility for low-power applications to integrate an efficient Adaptive Voltage Scaling (AVS) system on chip. Therefore the impact of process (both global and local), voltage and temperature variations is firstly studied on two typical low-power circuits i.e., a mobile processor and a wireless sensor node. In order to ensure safe operation under all conditions, it is required to increase the supply voltage by up to 22% leading to a nearly 50% increase in dynamic power consumption when compared to theoretical operating conditions. AVS allows for reducing the supply voltage guard band. To be able to include the AVS system on chip using standard CMOS, this paper proposes to use a switched-capacitor network for DC/DC conversion from the higher battery voltage. A critical path replica is used for both sensing the circuit maximum operating frequency and generating its clock signal. We show that the voltage ripple induced by the DC/DC converter does not significantly contribute to the supply voltage guard band, and that overall the proposed AVS system allows a reduction by up to 80% of this guard band while consuming less than 33% of the total circuit area.

A 65nm 1V to 0.5V linear regulator with ultra low quiescent current for mixed-signal ULV SoCs

The development of wireless sensor nodes (WSNs) as well as the rise of the Internet-of-Things (IoT) push ahead the research effort in ultra-low-power integrated circuits. Jointly with the recent development of micro-energy harvesters, it extends the battery lifetime of IoT nodes. Nevertheless, the power extracted by such energy harvesters does not provide a large power budget so that circuits in IoT nodes are highly duty cycled. In this paper we study switched-capacitor DC/DC converters as a solution for empowering such IoT nodes in a SoC integration. We specifically give insights about their sizing and show that a systematic sizing methodology is a strong tool enabling fast exploration of the design trade-offs. We also study how multi-mode converters can meet the power needs of IoT SoCs.

Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications

A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.

A ΔVt 0.2V to 1V 0.01mm 2 9.7nW voltage reference in 65nm LP/GP CMOS

Power-gating enables low stand-by power for high-speed applications. In this paper, we exploit the unique feature of quasi-double gate (QDG) mode MOSFETs in UTBB SOI to boost the performances of the power-gating sleep transistor. According to experimental results on a 10-nm BOX, at nominal Vg QDG mode enables up to 35% width and thereby leakage reduction for the sleep transistor. At circuit level, a charge pump architecture is proposed to generate the QDG back-gate bias for a 100-mA power-gated CPU with sub-100 ns wake-up/sleep times and negligible power/area overheads.

A 0.48mm 2 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage

Ultra-Low-Voltage (ULV) System-on-a-Chips (SoCs) are a growing research interest to fulfil the energy efficiency requirements of the wireless sensor node applications featuring sleep power below 1μW. ULP mixed-signal SoCs require a voltage reference robust to temperature, supply voltage and process variations. We propose a 9.7nW voltage reference based on a ΔVT architecture in 65nm LP/GP CMOS. Silicon measurements demonstrate functionality down to a record breaking 0.2V supply voltage.