Ryosuke Yamamoto

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated.

A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop

We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the low-power (ACFF) and the highly-reliable (BCDMR) flip-flops. Its power dissipation is almost equivalent to the transmission-gate FF at 10% data activity while paying 3 × area penalty. Experiments by α-particle and neutron irradiation reveal its highly-reliable operations with no error at 1.2 V and 1 GHz. We measured five different process corner chips by α irradiation. Soft error rates are almost equivalent in these corner chips.

Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops

Parasitic bipolar effects are intentionally used to prevent a simultaneous flip of redundant FFs, which make them more fault-resilient to soft errors. Device simulations reveal that a simultaneous flip of redundant latches is suppressed by storing the opposite values instead of storing the same value due to its asymmetrical structure. The state of latches always becomes a specific value after a particle hit due to the bipolar effects. Spallation neutron irradiation proves that no MCU is observed in the D-FF arrays in which the stored values of latches are equivalent to the specific value. The redundant latch structure storing the opposite values is robust to the simultaneous flip.

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm

We measures and investigate the correlation between well potential and SEUs to effectively detect SEUs by well potential perturbation. Cell-based perturbation detectors are implemented adjacent to FFs constructed a shift register. They measures the locations of voltage levels over 0.6 or 0.8 V. The measurement results by neutron irradiation on a 65nm bulk CMOS shows that almost 90% of SEUs are generated without any well potential perturbation. We also shows that the well-potential elevation over 0.8 V activates bipolar actions on neighbourhood transistors which prevents SEUs.

Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates

We measure neutron-induced SET (Single Event Transient) pulse width distributions from inverter chains with four drive strengths in a 65-nm CMOS process. The SET rates on 16x inverters are 17% and 38% of those on 1x in the twin-and triple-well structures respectively. Our measured results are in line with circuit simulation results that account for bipolar amplification. For higher SET mitigation, clock buffers could be placed adjacent to tap cells to reduce the number of SET pulses caused by the parasitic bipolar effect.

Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm

We measure and investigate the relationship between well potential perturbation and multiple cell upsets (MCUs) by neutron irradiation. Area-efficient cell-based perturbation detectors are placed adjacent to FFs (Flip-Flops). They can measure duration time of perturbation with 5 μm spatial resolution at two voltage levels. The measurement results by neutron irradiation on a 65-nm bulk CMOS show that 95% of MCUs occur simultaneously with well-potential perturbation, while there is very weak relationship between single event upsets (SEUs) and the perturbation.