Kuiyuan Zhang

Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops

Parasitic bipolar effects are intentionally used to prevent a simultaneous flip of redundant FFs, which make them more fault-resilient to soft errors. Device simulations reveal that a simultaneous flip of redundant latches is suppressed by storing the opposite values instead of storing the same value due to its asymmetrical structure. The state of latches always becomes a specific value after a particle hit due to the bipolar effects. Spallation neutron irradiation proves that no MCU is observed in the D-FF arrays in which the stored values of latches are equivalent to the specific value. The redundant latch structure storing the opposite values is robust to the simultaneous flip.

Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process

Technology scaling increases the role of charge sharing and bipolar effect with respect to multiple cell upset. We analyze the contributions of cell distance and well-contact density to suppress MCU by device-level simulations and neutron experiments. Device simulation results reveal that the ratio of MCU to SEU exponentially decreases by increasing the distance between redundant latches. MCU is suppressed when well contacts are placed between redundant latches. Experimental results also show that the ratio of MCU to SEU exponentially decreases by increasing the distance between cells. MCU is suppressed effectively by increasing the density of well contacts.

Contributions of charge sharing and bipolar effects to cause or suppress MCUs on redundant latches

There are two of main factors, charge sharing and bipolar effects to cause or suppress SEUs and MCUs. Technology scaling increases the the role of bipolar effects with respect to multiple bit upsets. We analyze contributions of charge sharing and bipolar effects by changing the position of well contacts and the well structure. Device simulation results reveal that charge sharing and bipolar effect are suppressed effectively when the well contacts are placed in the middle of two latches.

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) FD-SOI processes. Soft errors are induced by alpha-particle and neutron irradiation and the results are then analyzed by Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section and neutron-induced soft error rate (SER) obtained by simulation are consistent with measurement results. We clarify that SERs decreased in response to an increase in the BOX thickness for SOTB while SERs in UTBB are independent of BOX thickness. We also discover SOTB develops a higher tolerance to soft errors when reverse body bias is applied while UTBB become more susceptible.

Impact of body bias on soft error tolerance of bulk and Silicon on Thin BOX structure in 65-nm process

We analyze the soft error tolerance of DFF in 65-nm bulk and SOTB (Silicon on Thin BOX) process by alpha and neutron experiments and device-simulations. The experimental results reveal that by increasing the reverse body bias the soft error rate in the bulk structure is increased, while the number of soft errors in SOTB structure is decreased. The results from device-simulation show that the collected charge of bulk structure is increased, while the collected charge is decreased in SOTB as the reverse body bias increases.

Analysis of the soft error rates on 65-nm SOTB and 28-nm UTBB FD-SOI structures by a PHITS-TCAD based simulation tool

We estimate the SERs of 65-nm SOTB(Silicon on Thin BOX) and 28-nm UTBB(Ultra Thin Body and BOX) FD-SOI processes by decreasing the supply voltage. Alpha, neutron irradiation experiments and Monte-Carlo based simulations are compared in this work. The SERs can be analyzed by the simulation tool with only layout pattern of test chips. The simulation results are consistent with the alpha and neutron irradiation measurement results.

Analysis of BOX Layer Thickness on SERs of 65 and 28nm FD-SOI Processes by a Monte-Carlo Based Simulation Tool

We estimate SERs of FD-SOI structures according to the thicknesses of BOX (Buird OXide) layer on 65-nm and 28-nm processes by reducing supply voltage. Alpha, neutron irradiation experiments and Monte-Carlo based simulations are compared in this work. The SOTB (Silicon on Thin BOX) and the UTBB (Ultra Thin Body and BOX) structures are evaluated in the irradiation experiments. The SERs of those structures are analyzed by the simulation tool with layout pattern of test chips. The simulation results are consistent with the alpha and neutron irradiation measurement results. According to the simulated result, the SERs are decreased by increasing the thickness of BOX layer.

Estimation of Soft Error Tolerance According to the Thickness of Buried Oxide and Body Bias 28-nm and 65-nm in FD-SOI Processes by a Monte-Carlo Simulation

1. Abstract We estimate the soft error rates of FD-SOI structures according to the thicknesses of BOX(Buird OXide) layers and body bias on 65-nm and 28-nm processes by reducing the supply voltage. A Monte-Carlo based simulation is used in this work. The parasitic bipolar effect is suppressed by thicker BOX on FD-SOI structure.The simulation results are consistent with the alpha and neutron irradiation measurement results. We will show the SERs of FD-SOI structures according to the body bias in the final paper.