Kazuya Ishihara
Renesas Electronics
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Featured researches published by Kazuya Ishihara.
custom integrated circuits conference | 2001
Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shinichi Hattori; Atsushi Koshio; Kazuhiro Tsukamoto; Tetsuva Matsumura
A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.
custom integrated circuits conference | 1998
Atsuo Hanami; Stefan Scotzniovsky; Kazuya Ishihara; Tetsuya Matsumura; T Shin-ichi Takeuchi; T Haruyuki Ohkuma; Koji Nishigaki; Hirokazu Suzuki; Masahiro Kazayama; Toyohiko Yoshida; Koji Tsuchihashi
A wide range motion estimation with exhaustive search is the best approach for high quality encoding applications. To perform the required computational power, a 165 GOPS (giga operations per second) exhaustive motion estimation processor ME3 has been developed. The ME3 is powerful enough to realize a range of -64/+63 pixels horizontally and -32/+31 pixels vertically with a single chip. A dual-array architecture supports not only high calculation power but also luminance and chrominance based search to increase picture quality. Also, the ME3 outputs extra vectors as candidates to enhance the picture quality. Using a multi-chip configuration, the exhaustive search range can be easily expanded to meet the requirements of MP@HL encoder. It is implemented using 0.35 /spl mu/m CMOS technology and contains 1.9 million transistors in an area of 8.5/spl times/8.5 mm/sup 2/.
symposium on cloud computing | 2010
Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Hirofumi Nakano; Kazuya Ishihara; Hiroyuki Kawai; Kazutami Arimoto
We present a fine-grained assist bias control technique for enhancing read-/write-margins of embedded SRAM in deep-submicron SoC. This technique controls the individual assist bias for finely segmented rows and columns of a cell array with small area overheads. We design and fabricate prototype micro-controller test chips with 1 Mb SRAM using 90-nm low-standby-power CMOS technology. The evaluation results demonstrate that Vmin achieves 0.64 V, which is a 21% improvement compared to the conventionally used technique.
custom integrated circuits conference | 1999
Satoshi Kumaki; Tetsuya Matsumura; Kazuya Ishihara; Hiroshi Segawa; K. Kawamoto; H. Ohira; T. Shimada; Hidenori Sato; T. Hattori; T. Wada; H. Honma; T. Watanabe; K. Asano; Toyohiko Yoshida
A single chip MPEG2 video, audio, and system encoder for various applications such as PC authoring, DVD-recorder and digital TV has been described. It performs real-time 422@ML video encoding, Dolby Digital (AC-3)/MPEG1 audio encoding, and system encoding which multiplexes the video and audio streams and generates a transport stream or a program stream. The encoder LSI employs an advanced hybrid architecture with a 162-MHz media-processor and dedicated video processing hardware. This architecture not only realizes a complete encoder but also achieves the high flexibility required for improving picture quality. Dual motion estimation cores, fine ME for high search precision and coarse ME for a wide search range, are integrated for optimal motion vector search. The encoder LSI is implemented using 0.25 micron four-metal CMOS technology and integrates 11 million transistors in an area of 14.2/spl times/14.2 mm/sup 2/.
The Japan Society of Applied Physics | 1993
Shigeo Ohnishi; Masaya Komai; Kazuya Ishihara; Keizo Sakiyama Masaru Shimizu; Tadashi Shiosaki
Thls_paper describes the oxygen enhanced dissociation effect of Pb precursors for high-quality MOCVD-WI thin frlm. Bisdipivaloylmethanate lead for Pb soruce material is easily decomposed between Pb and oxygen bond, causing the poor PbO formation. This generates the Pb-poor phase 4 the initial stage of PTII deposition. By enough oxygen gas supply to form PbO sufficiently, the fine surface morphology and the excellent crystallinity are obtained. As a result, excellent polarizationproperties(Pr = 23.6Stclcm2, = 838) are achieved and it enables the application for 1664 Mbit FRAMs. s-tv-8
Archive | 1999
Atsuo Hanami; Tetsuya Matsumura; Satoshi Kumaki; Kazuya Ishihara
IEICE Transactions on Electronics | 1995
Masahiko Yoshimoto; Shinichi Nakagawa; Tetsuya Matsumura; Kazuya Ishihara; Shinichi Uramoto
Archive | 1999
Toyohiko Yoshida; Kazuya Ishihara; Yoshinori Matsuura; Tetsuya Matsumura
IEICE Transactions on Electronics | 2001
Tetsuya Matsumura; Satoshi Kumaki; Hiroshi Segawa; Kazuya Ishihara; Atsuo Hanami; Yoshinori Matsuura; Stefan Scotzniovsky; Hidehiro Takata; Akira Yamada; Shu Murayama; Tetsuro Wada; Hideo Ohira; Toshiaki Shimada; Kenichi Asano; Toyohiko Yoshida; Masahiko Yoshimoto; Koji Tsuchihashi; Yasutaka Horiba
Archive | 2000
Kazuya Ishihara; Hiroshi Segawa