Shigeo Onishi

Barrier properties for oxygen diffusion in a TaSiN layer

Annealing in O2 at temperatures above 650° C is required for a thin ferroelectric capacitor. Reduction of the leakage current and an increase of capacitance can be attained in the charge storage capacitor through this annealing. A stacked structure capacitor cell must be practically employed in metal oxide semiconductor large scale integrated circuits (MOSLSI). In this capacitor cell with a conventional Pt/TiN/poly-Si lower electrode, however, O2 annealing can not be attained at high temperature because peeling of the TiN barrier layer and the formation of a thin oxide layer at the surface of poly-Si occur. An noncrystalline TaSiN layer has been studied with respect to the barrier effect for oxygen diffusion used in the barrier layer of the lower electrode. The penetration depth of oxygen diffusion decreases markedly with increasing Si composition in a TaSiN layer and reaches 20 nm deep in a Ta.22Si.35N.43 layer. However, the resistivity increases with this increase. A good diffusion barrier layer with low sheet resistance is attained in a Ta.50Si.16N.34 layer. Penetration depth below 40 nm is obtained in a slightly Si-rich Ta.36Si.27N.37 layer for O2 annealing at 850° C.

Barrier Effect of TaSiN Layer for Oxygen Diffusion

The barrier effect for oxygen diffusion is studied in TaSiN layers. The TaSiN is deposited by reactive sputtering employing Ta and Si targets. The composition of the layer ranges from Ta{sub 0.16}Si{sub 0.27}N{sub 0.57} to Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} by varying the Ta target power from 100 to 400 watts (W). A resistivity of 210 {micro}{Omega} cm is obtained for the Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} layer. The surface oxidation and in-diffusion of oxygen to a depth of 15 nm into the Ta{sub 0.30}Si{sub 0.17}N{sub 0.53} layer are observed by annealing in O{sub 2} at 650 C. However, the oxygen diffusion is suppressed in the Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} layer. No out-diffusion of oxygen occurs from the Ta{sub 2}O{sub 5} dielectric layer to the amorphous barrier layer. This result shows that a low Si concentration layer for instance, Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} is a promising barrier layer for oxygen diffusion and is useful for charge storage capacitors for MOS memory devices.

Formation of a defect-free junction layer by controlling defects due to As/sup +/ implantation

A method of suppressing defects related to knock-on has been developed through the use of a Si/sub 3/N/sub 4/ film as an implementation mask. In MOS devices with LDD structures, junction leakage is caused by the dislocation lines from the sidewall edge. Two requirements are needed to suppress the growth of the dislocation lines: the elimination of stress from the sidewall edge and the elimination of dislocation loops due to As/sup +/ implantation. The growth of dislocation loops is affected by the presence of recoiled oxygen atoms from implantation through SiO/sub 2/ films. However, when a Si/sub 3/N/sub 4/ mask is used as an implantation mask, the amount of recoiled nitrogen atoms is two orders of magnitude lower in comparison to the recoiled oxygen atoms for a SiO/sub 2/ mask, and the dislocation loops disappear during heat treatment. Consequently, defects are not generated and the junction leakage failures due to residual defects disappear.<<ETX>>

High Temperature Barrier Electrode Technology for High Density Ferroelectric Memories with Stacked Capacitor Structure

This paper describes the novel stacked electrode structure, PtRhO x /PtRh/PtRhO x , applicable to stacked memory cells in advanced ferroelectric memories. This structure acts as a stable bottom electrode and a barrier on a polysilicon plug up to 700°C and a stable contact resistance of 1.5 KΩ is obtained at the contact size of 0.6 μm. In addition to the low leakage current of lead zirconate titanate [PZT, Pb(Zr 0.52 Ti 0.48 )O 3 ] capacitor (10 8 A/cm 2 at 3 V), degradation properties of fatigue and imprint are improved compared with conventional Pt electrodes. The decrease of the switched charge is restricted to less than 10% after the fatigue cycle of 10 11 . These results indicate its promise as a barrier electrode structure for advanced ferroelectric memory integration.

Defect-free shallow P/N junction by point defect engineering

By taking advantage of high-stress SiN/sub x/ film as a source of vacancies, a defect-free shallow junction technology was developed by point defect engineering. By depositing the SiN/sub x/ film with high stress (1*10/sup 10/ dyn/cm/sup 2/) and annealing the sample, the vacancies were supplied from the SiN/sub x/-Si interface into the Si substrate to relax the stress of the SiN/sub x/ film and react with the extrinsic defect due to implantation. The density of the defects was then one order of magnitude lower than the sample without the SiN/sub x/ film. This technology is also useful for reducing the diffusion of dopant, which is controlled by the interstitial Si atoms. It was confirmed that the dopant profile of B+ was also shallower by about 10%.<<ETX>>

A New Method For Evaluating Temperature Distribution By Using Si + + B + Implantation

A method for evaluating temperature distributions between 400 °C and 600 °C have been studied by utilizing Si+ + B+ implantation. From the measurement of the sheet resistance(ps ), the equations shown in ps =3.8x10-8( t )-0.6 exp(Ea / kT) (Furnace anneal), Ps = 9.0x10-9( t )-0.5 exp( Ea / kT) (RTA) are obtained. And an obtained activation energy ( Ea) of 1.9eV is equivalent to that of solid phase epitaxial regrowth. From the distribution of the sheet resistance, the estimation of the temperature distribution between 400°C and 600 °C becomes possible for annealing times from lsec. to lhour.

A SiO/sub x/ resistor load SRAM process for ASIC applications

A silicon oxide film that has been heavily doped with phosphorus and silicon by ion implantation through a capping polysilicon layer has been studied for use as a high-resistance load device in a static random-access memory (SRAM). The fabrication process needs the addition of only one extra mask, for the ion implantation, in the standard CMOS process. The resistance per square micrometer is more than 1 T Omega under 5-V bias. The temperature dependence of this resistor is significantly improved in comparison with the lightly-doped polysilicon resistor which is widely used in SRAMs. An estimated breakdown lifetime in the actual working current density range is more than 100 years at temperatures up to 140 degrees C.<<ETX>>

Low Damage Magnetron Enhanced Reactive Ion Etching

Damage formation mechanism of Magnetron Enhanced Reactive lon Etching (MERIE) and the ways to suppress etching damage have been investigated. Deep damaged layers are induced by light weight ions such as C, F and H formed by the decomposed from the reactant gases in the magnetic field. Damage formation in MERIE is closely related to plasma density. However low damage etching has been achieved by using high molecular weight fluorocarbon compounds as etching gascs. PB.2.4