Juncheng Wang

RRAM Crossbar Array With Cell Selection Device: A Device and Circuit Interaction Study

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I-V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.

Physically Based Evaluation of Electron Mobility in Ultrathin-Body Double-Gate Junctionless Transistors

In this letter, we presented theoretical results on the low-field electron mobility of ultrathin-body double-gate junctionless transistors. A 1D Poisson-Schrödinger problem perpendicular to the gate is self-consistently solved to get the electron wavefunctions, and the Kubo-Greenwood formula with consideration of phonon, surface roughness, and ionized impurity scattering is employed to evaluate the corresponding mobility components. The dependence of mobility on silicon layer thickness and doping concentration is also investigated.

Mixed-Mode Analysis of Different Mode Silicon Nanowire Transistors-Based Inverter

In this paper, we focused on the comparison and analysis of the performance of inversion-mode (IM), accumulation-mode (AM), and junctionless (JL) silicon nanowire field-effect transistors (NWTs)-based inverter. The effects of the radius, equivalent oxide thickness and source/drain doping in the different mode nanowire device structure are investigated. The capacitance components and transient characteristics, which determine the behavior of devices in the circuits, are studied and compared among different mode nanowire devices. The mixed-mode circuit simulations have been performed for the inverter circuit and three-stage ring oscillator consist of n-type and p-type IM/AM/JL NWTs. JL NWTs show lower Miller capacitance which contributes to suppressing the overshoot effect in the circuits. Results of these simulations can give insights into the in-circuit behavior of these future generation devices.

Finite-Size Effects on Thermionic Emission in Metal–Graphene-Nanoribbon Contacts

A finite-size effect leads to more electrons to occupy high-energy states in a graphene nanoribbon. Therefore, the thermionic-emission (TE) current density of a metal/graphene nanoribbon changes with its width when the graphene nanoribbon is a semiconductor. This letter demonstrates that the TE current density increases rapidly with the decreasing width of the graphene nanoribbon. It is also found that the finite-size effect on TE current density is more significant at low temperatures.

Investigation of self-heating effect in SOI-LDMOS by device simulation

Self-heating effect in SOI-LDMOS power devices has become a repeated discussion as the active silicon layer thickness is reduced and buried oxide layer thickness is increased. Heat dissipation and the self-heating effect become critical issues of SOI power devices. In this paper, simulations of self-heating effect under different thermal boundary conditions are performed. The influence of difference device parameters, including BOX (Buried OXide) thickness, trench length, SOI (Silicon On Insulator) thickness, source/drain lumped surface thermal resistance, are simulated to investigate their impact on self-heating effect. The work is intended to provide reference for device design and the optimization of source/drain contact in consideration of self-heating effect.

Investigation of terahertz plasma oscillations in nano-scaled double-gate MOSFETs by Monte Carlo method

In this paper, we investigate the terahertz plasma oscillations in nano-scaled double-gate n-type Silicon MOSFET with 2D ensemble Monte Carlo simulation method. The effects of the drain-to-source biases, gate-to-source biases and doping levels in the source/drain regions of the devices on the terahertz plasma oscillations are considered. The relation between terahertz plasma oscillations and the channel scaling in double-gate MOSFET is also discussed. The oscillation frequency peak value as a function of doping levels exhibits a good agreement with the predictions of 2D plasma frequency.

Investigation of local heating effect for 14nm Ge pFinFETs based on Monte Carlo method

FinFET is regarded as one of the most promising device structure for future scaling-down demands. However, heat dispassion is a severe problem for the device performance and reliability in nano-scale FinFETs. Germanium (Ge) is a novel channel material with its high carrier mobility, especially for PMOSFET. However, the bulk thermal conductivity of Ge (52.98Wm-1K-1) is almost 3 times smaller than that of Si (148.6Wm-1K-1)[1], which will lead to more serious heat dispassion problems in Ge devices. Whats more, the phonon mean free path is largely decreased in nano-device structure due to increased surface scatterings, which leads to a largely reduced thermal conductivity. Hence, heat dissipation problems will have a large impact on the performance of Ge FinFETs. In this paper, we use 3D Full Band Self-consistent Ensemble Monte Carlo Simulator and 3D Fourier Heat Conduction Solver to study the local heating effects (LHE) and its impact on 14nm Ge SOI pFinFETs. The heat dissipation path is also evaluated. From the simulation results, we find that 14nm Ge SOI FinFETs will experience severe heating problems and heat effects will seriously affect the device performance.

Monte Carlo investigation of Silicon MOSFET for terahertz detection

In this paper, the terahertz (THz) detection based on Silicon MOSFET is investigated with two-dimensional (2D) ensemble Monte Carlo (MC) simulation study. The analytical model of responsivity to high frequency small signals based on the small-signal equivalent circuit of MOSFETs operating in terahertz detection mode are developed and calibrated. We explore the impacts of input excitation signals with different frequency and amplitude on THz detection. Moreover, it is shown that the responsivity to THz excitations could be controlled by modulation of the gate voltage and the gate length in the MOSFET.

Simulation of band-to-band tunneling in Si/Ge and Si/Si 1−x Ge x heterojunctions by using Monte Carlo method

In this paper, we investigate the band-to-band tunneling (BTBT) in Si/Ge and Si/Si1-xGex heterojunctions by employing a two-dimensional (2D) full band Monte Carlo (FBMC) heterojunction simulator. The FBMC simulator is used to get the electrostatic potential and field in a heterojunction, based on which we can calculate the BTBT rate and current by Hurkxs tunneling model. The model parameters have been carefully calibrated to reproduce the experimental reverse current in a Si p-n junction. With this framework, it is shown that the BTBT current in the Si/Ge or Si/Si1-xGex heterojunction is largely enhanced when compared with conventional Si homojunctions. We ascribe this to the smaller bandgap of Ge and the SiGe alloy than that of Si. It is further found that whether the smaller bandgap material is used as the relative lower or higher doping side of the heterojunction is much different. The former can produce a BTBT current significantly larger than that of the latter.

Performance investigation on the reconfigurable Si nanowire schottky barrier transistors

In this paper, the performance of the reconfigurable Si nanowire Schottky barrier transistors (RFETs) is investigated with simulation method. In contrast to conventional Schottky barrier MOSFETs (SB-MOSFETs) and silicon nanowire transistors (Si-NWTs) with metal/silicide as source/drain, the separate two gates in RFETs are located at the two Schottky junctions. Our simulation results show the variable electric characteristics and working principle of the RFETs working as p-/n-type. The RFETs exhibit higher on/off current ratio compared with other Schottky transistors.