Zhiyuan Lun

Atomic Monte-Carlo simulation for CBRAM with various filament geometries

An atomic Monte-Carlo simulator of Conductive Bridge Random Access Memory (CBRAM) is developed to investigate the microscopic properties of filament growth and dissolution during Forming/SET and RESET processes. The cluster growth during nucleation correlated with electrochemical reactions and cations transportation are included. The impacts of the critical material parameters on the geometry of conductive filaments (CF) are clarified by the simulator. The conical and dendrite shape CF experimentally observed by different groups are simulated by tuning the critical material parameters. Using the simulator, the microscopic properties of Forming/SET and RESET processes with different CF geometries are investigated and the retention behaviors can be analyzed.

Investigation of retention behavior for 3D charge trapping NAND flash memory by 2D self-consistent simulation

This paper presents a comprehensive investigation on retention behavior for three-dimensional charge trapping NAND flash memory by two-dimensional self-consistent simulation. Major physical mechanisms, including tunneling, charge trapping and de-trapping process as well as drift-diffusion have been incorporated into the simulator. The developed simulator is able to describe the charge transport along the bitline and in vertical direction in the memory structure. This work aims to help to design and optimize three-dimensional stackable CT-NAND architectures.

Investigation of self-heating effect in SOI-LDMOS by device simulation

Self-heating effect in SOI-LDMOS power devices has become a repeated discussion as the active silicon layer thickness is reduced and buried oxide layer thickness is increased. Heat dissipation and the self-heating effect become critical issues of SOI power devices. In this paper, simulations of self-heating effect under different thermal boundary conditions are performed. The influence of difference device parameters, including BOX (Buried OXide) thickness, trench length, SOI (Silicon On Insulator) thickness, source/drain lumped surface thermal resistance, are simulated to investigate their impact on self-heating effect. The work is intended to provide reference for device design and the optimization of source/drain contact in consideration of self-heating effect.

A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory

This work presents a self-consistent two-dimensional (2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data, which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.创新点本文介绍了可用于研究三维电荷俘获存储器的二维自洽模拟方法。该方法使用了统一的物理模型, 可对电荷存储器的各个工作模拟进行模拟。该模拟方法考虑了载流子的隧穿过程、电荷俘获发射机制, 以及在电荷存储层中的二维漂移-扩散模型, 并且同时对一条位线上相邻的三个存储单元进行模拟。本文开发的模拟器同时考虑了沿位线和隧穿两个方向的电子输运, 可用来研究不同栅叠层存储器件在多种温度下的电子输运行为。

Two-dimensional self-consistent simulation on program/retention operation of charge trapping memory

This paper presents a two dimensional numerical simulation on the program and retention operation of charge trapping memory. The developed simulator self-consistently solves two-dimensional Poisson equation, carrier continuity equation and trapped charge conservation equation. Drift-diffusion transport scheme is used for modeling the charge transport in the trapping layer. Major physical models, such as, direct, band-to-trap, trap-to-band tunneling and carrier capture and emission are incorporated into the simulator. The numerical simulation is able to study the programming and retention performance of charge trapping memory under different temperatures two-dimensionally. The simulation aims to investigate memory devices in scaled structures and especially in 3D applications.

Simulation on endurance characteristic of charge trapping memory

A comprehensive simulation method for endurance reliability issues in charge trapping memory is developed. For this purpose, a practical algorithm is carefully designed to investigate the cycling performance of charge trapping memory. The models that account for the generation of substrate/tunneling oxide interface trapped charge and oxide trapped charge are incorporated into the simulation. The influence of these models on flat-band voltage evolution under programing/erasing cycling is investigated in detail, thus providing insight into the mechanism of the endurance issues in charge trapping memory.

Insight into PBTI in InGaAs nanowire FETs with Al 2 O 3 and LaAlO 3 gate dielectrics

The traps induced degradation of the Al<inf>2</inf>O<inf>3</inf> and LaAlO<inf>3</inf> based InGaAs nanowire FETs are investigated by 3D Kinetic Monte-Carlo (KMC) method considering trap coupling and trap generation. The measurement time constants of the defect in Al<inf>2</inf>O<inf>3</inf> and positive bias temperature instability (PBTI) can be well interpreted by consideration with metastable state. The power law of threshold shift can be greatly affected by the stress. Different from traps in Al<inf>2</inf>O<inf>3</inf>, oxygen vacancies and interstitial Aluminum ions in LaAlO<inf>3</inf> have important roles in PBTI. Simulated results indicate that Al<inf>2</inf>O<inf>3</inf> have better PBTI and recovery than that of LaAlO<inf>3</inf>.

Investigation of scattering mechanism in nano-scale double gate In 0.53 Ga 0.47 As nMOSFETs by a deterministic BTE solver

We investigate the scattering mechanism in ultrashort double gate In0.53Ga0.47As nMOSFETs by deterministically solving Boltzmann transport equation (BTE). The intra-valley acoustic phonon scattering, optical phonon scattering, intervalley optical scattering, polar optical scattering, and surface roughness (SR) scattering are considered. The impacts of scattering on the performance of device under high/low biases are compared. Results show that the ballistic ratio (Iscat/Iball) decreases from 96.8% to 94.5% when the drain bias increases from 0.05V to 0.6V, which is mainly caused by the inter-valley scatterings.

Evaulation the degradation in nMOSFETs with HfO 2 gate dielectric and interfacial layer by 3D Kinetic Monte-Carlo method

This paper evaluates the degradation process in nMOSFETs with HfO2 gate dielectric and interfacial layer (IL) by 3D Kinetic Monte-Carlo (KMC) method considering multi-trap coupling. The degradation and corresponding trap evolution in a 1-nm EOT dielectric stack with different thicknesses of SiO2 IL is simulated under different gate biases (Vg) and temperature (T). The results indicate that IL can suppress the positive bias temperature instability (PBTI) but increase the gate leakage and weaken the capability to endure stress.

Simulation method for forming and switching processes of NbO2-based selector

NbO2-based selector with threshold switching characteristics was studied as a probable candidate to address the sneak-path problem in the resistive-switching random access memory(RRAM) arrays. In this work, we simulate the forming and switching process of the selector with consideration of the thermally driven metal-insulator transition and crystallization effects. Based on the simulator, we analyze the influence and optimization of the working conditions and device dimensions on the device characteristics.