Jung-Hoe Choi

Cost effective solution using inverse lithography OPC for DRAM random contact layer

Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics. This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.

Layout optimization with assist features placement by model based rule tables for 2x node random contact

As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. There are known-well several methods to generate SRAF such as Rule based Assist Features (RBAF), Model Based Assist Features (MBAF) and Hybrid Assisted Features combining features of the different algorithms using both RBAF and MBAF. Rule Based Assist Features (RBAF) continue to be deployed, even with the availability of Model Based Assist Features (MBAF) and Inverse Lithography Technology (ILT). Certainly for the 3x nm node, and even at the 2x nm nodes and lower, RBAF is used because it demands less run time and provides better consistency. Since RBAF is needed now and in the future, what is also needed is a faster method to create the AF rule tables. The current method typically involves making masks and printing wafers that contain several experiments, varying the main feature configurations, AF configurations, dose conditions, and defocus conditions – this is a time consuming and expensive process. In addition, as the technology node shrinks, wafer process changes and source shape redesigns occur more frequently, escalating the cost of rule table creation. Furthermore, as the demand on process margin escalates, there is a greater need for multiple rule tables: each tailored to a specific set of main-feature configurations. Model Assisted Rule Tables(MART) creates a set of test patterns, and evaluates the simulated CD at nominal conditions, defocused conditions and off-dose conditions. It also uses lithographic simulation to evaluate the likelihood of AF printing. It then analyzes the simulation data to automatically create AF rule tables. It means that analysis results display the cost of different AF configurations as the space grows between a pair of main features. In summary, model based rule tables method is able to make it much easier to create rule tables, leading to faster rule-table creation and a lower barrier to the creation of more rule tables.

Numerical analysis for resist profile after thermal process in display manufacturing

The screen size growth of mobile displays is accompanied with the drastically increased resolution. A display should have high pixel resolution to meet demanding readability and legibility expectations. The manufacturing process should be advanced to meet final device requirements. One of the important process steps is the post-development hardbake, where resist reflow is used to tune the final profile which influences subsequent process steps. Moreover, 3D resist profiles become one of critical design factors for mechanical and optical properties of display pixels. The resist reflow is the main time- and temperature-dependent effect of post-development bake process step. Since the resist is in transitional state (crystalline glassy/amorphous rubbery/viscous melt) the resist profile dynamics are very complex and predictive modeling is necessary. The model presented in this paper is based on a lattice-Boltzmann method, where the resist is considered as multicomponent (polymer-solvent) and multiphase (solid-liquid-vapor) mixture. Simulated resist profile dynamics with time are analyzed in dependency of material parameters (solvent diffusivity and evaporation rate, polymer solid fraction and adhesion with substrate). Temperature-dependent parameter descriptions are used for model calibration. Validation against experimental data shows good model consistency and predictability, demonstrating the benefit of simulation in process development and optimization.

Layout optimization of DRAM cells using rigorous simulation model for NTD

DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.

Mask compensation for process flare in 193nm very low k1 lithography

Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.

Process window analysis of algorithmic assist feature placement options at the 2X nm Node DRAM

As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based (MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall solution. RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only on the very local geometric environment, which is important in applications where consistent signal propagation is of critical importance. MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows for efficient investigations of future technology nodes as the number of interactions between local layout features increases beyond what RBAF algorithms can effectively support Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement options might result in relatively improved process window compared to an independent approach since two methods are capable of supplement each other with a complementary advantages. In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to process window.

Model-driven target optimization to resolve design hotspots through image quality enhancement

Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2- dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process variation band and the pitches of hotspot points are relaxed.The image quality improvement is thenchecked. Model driven target optimized NILS and MEEF at the weakest hotspot point are improved to 1.22 and 5.5 from the values 0.79 and 10.6 of a traditional OPCwith advanced solver, respectively. The pattern collapsing hotspot is then validated to be repaired by optimizing target position. A full hotspot fixer flow including model-driven target optimization using ILT can also be extended into DFM applications.

Improvement on post-OPC verification efficiency for contact/via coverage check by final CD biasing of metal lines and considering their location on the metal layout

As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by k1 factor. To guarantee the imaging fidelity, resolution enhancement technologies (RET) such as off-axis illumination (OAI), different types of phase shift masks and OPC technique have been developed. In case of model-based OPC, to cross-confirm the contour image versus target layout, post-OPC verification solutions continuously keep developed - contour generation method and matching it to target structure, method for filtering and sorting the patterns to eliminate false errors and duplicate patterns. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process - to save not only reviewing time and engineer resource, but also whole wafer process time and so on. In general case of post-OPC verification for metal-contact/via coverage (CC) check, verification solution outputs huge of errors due to borderless design, so it is too difficult to review and correct all points of them. It should make OPC engineer to miss the real defect, and may it cause the delay time to market, at least. In this paper, we studied method for increasing efficiency of post-OPC verification, especially for the case of CC check. For metal layers, final CD after etch process shows various CD bias, which depends on distance with neighbor patterns, so it is more reasonable that consider final metal shape to confirm the contact/via coverage. Through the optimization of biasing rule for different pitches and shapes of metal lines, we could get more accurate and efficient verification results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using simple biasing rule to metal layout instead of etch model application is presented.

Score-based fixing guidance generation with accurate hot-spot detection method

While predicting and removing of lithographic hot-spots are a matured practice in recent semiconductor industry, it is one of the most difficult challenges to achieve high quality detection coverage and to provide designer-friendly fixing guidance for effective physical design implementation. In this paper, we present an accurate hot-spot detection method through leveling and scoring algorithm using weighted combination of image quality parameters, i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF) which can be obtained through lithography simulation. Hot-spot scoring function and severity level are calibrated with process window qualification results. Least-square regression method is used to calibrate weighting coefficients for each image quality parameter. Once scoring function is obtained with wafer results, it can be applied to various designs with the same process. Using this calibrated scoring function, we generate fixing guidance and rule for the detected hot-spot area by locating edge bias value which can lead to a hot-spot free score level. Fixing guidance is generated by considering dissections information of OPC recipe. Finally, we integrated hot-spot fixing guidance display into layout editor for the effective design implementation. Applying hot-spot scoring and fixing method to memory devices of the 50nm node and below, we could achieve a sufficient process window margin for high yield mass production.

Mask process effect aware OPC modeling

Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict the entire lithography process correctly even using advanced optical and resist models. In order to compensate for the mask proximity effect within OPC a special model is required along with changes to the OPC flow. This article presents a method for producing such a model and OPC flow and shows the difference in results when they are used.