Manhong Zhang

Investigation of resistive switching in Cu-doped HfO2 thin film for multilevel non-volatile memory applications

In this paper, the resistive switching characteristics in a Cu/HfO(2):Cu/Pt sandwiched structure is investigated for multilevel non-volatile memory applications. The device shows excellent resistive switching performance, including good endurance, long retention time, fast operation speed and a large storage window (R(OFF)/R(ON)>10(7)). Based on the temperature-dependent test results, the formation of Cu conducting filaments is believed to be the reason for the resistance switching from the OFF state to the ON state. By integrating the resistive switching mechanism study and the device fabrication, different resistance values are achieved using different compliance currents in the program process. These resistance values can be easily distinguished in a large temperature range, and can be maintained over 10 years by extrapolating retention data at room temperature. The integrated experiment and mechanism studies set up the foundation for the development of high-performance multilevel RRAM.

Formation of multiple conductive filaments in the Cu/ZrO2:Cu/Pt device

We report the direct electrical measurement of multiple resistance steps in the ZrO2-based solid electrolyte nonvolatile memory device using the refined dc I-V method with a very small voltage increasing rate. The results demonstrate that multiple conductive filaments are formed successively between the bottom and top metal electrodes through the insulating layer while increasing the bias voltage, which are consistent with the electrical field simulation results based on the solid electrolyte theory. The inverse relationship between resistance steps and the filament formation sequence are obtained, which helps understand the switching mechanism of the multiple conductive filaments.

Performance enhancement of multilevel cell nonvolatile memory by using a bandgap engineered high-κ trapping layer

A high-κ based charge trap flash (CTF) memory structure using bandgap engineered trapping layer HfO2/Al2O3/HfO2 (HAH) has been demonstrated for multilevel cell applications. Compared to a single HfO2 trapping layer, a CTF memory device based on the HAH trapping layer exhibits a larger memory window of 9.2 V, faster program/erase speed, and significantly improved data retention. Enhancements of memory performance and reliability are attributed to the modulation of charge distribution by bandgap engineering in trapping layer. The findings provide a guide for future design of CTF.

Low-Power and Highly Uniform Switching in

In this letter, the insertion of a Cu nanocrystal (NC) layer between the Pt electrode and ZrO2 film is proposed as an effective method to improve resistive switching properties in the ZrO2-based resistive switching memory. This Cu/ZrO2:Cu/Cu NC/Pt memory exhibits asymmetric nonpolar resistive switching behavior, low operating voltage (<; 1.2 V), low Reset current (<; 50 μA), and high uniformity of resistance switching. The switching mechanism is believed to be related with the formation and rupture of conductive filament. The NC-induced electrical field enhancement has the benefit to accelerate and control the CF formation process, thus leading to low-switching threshold voltage and high uniformity.

\hbox{ZrO}_{2}

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.

-Based ReRAM With a Cu Nanocrystal Insertion Layer

In this paper, we report a metal/Al2O3/ZrO2/SiO2/Si (MAZOS) structure with a ZrO2 charge-trapping layer for non-volatile memory application. The superiority of this device over the traditional metal/Al2O3/Si3N4/SiO2/Si (MANOS) devices is much better data retention and enhanced program/erase efficiency. The MAZOS device exhibits excellent memory characteristics, including a large memory window of 7.1 V under ±11 V capacitance–voltage sweep, and a greatly improved data retention (only 16% charge loss for 10 years time) along with good endurance. The MAZOS device has a strong potential for future high-performance non-volatile memory application.

A study of cycling induced degradation mechanisms in Si nanocrystal memory devices.

There are three basic multiphonon trap-assisted tunneling (TAT) mechanisms in the gate leakage current of a metal-oxide-semiconductor (MOS) structure: the short-ranged trap potential, nonadiabatic interaction and electric field induced trap-band transitions. In this paper, a comparison of these three mechanisms is made for the first time in a single (Schenk’s model) MOS structure. A properly box-normalized electron wave function in the SiO2 conduction band in an electric field is used to calculate the field ionization rate of a deep neutral trap. It is found that capture and emission rates of a deep neutral trap are almost the same in the short-ranged trap potential and nonadiabatic interaction induced TAT processes, so the two mechanisms give a similar contribution to the total TAT current. The calculated TAT current and the average relaxation energy (∼1.5 eV) due to these two mechanisms are in good agreement with the experimental results. In contrast, capture and emission rates in Schenk’s model are sev...

A metal/Al2O3/ZrO2/SiO2/Si (MAZOS) structure for high-performance non-volatile memory application

In this letter, we fabricate Cu/ZrO2:Au/Pt and Cu/ZrO2:Ti/Pt devices via implanting Au or Ti ions. We systematic investigate the resistance switching properties of the two types of metal doped ZrO2-based resistance random access memory. Compared with the undoped (Cu/ZrO2/Pt) device, the metal doped devices show free-electroforming process, narrow distribution of the switching parameters and high device yield. The formation and rupture of conductive filaments with metal ions or oxygen vacancies are suggested to be responsible for the resistive switching phenomenon. The doped Au or Ti impurities influence the distribution and concentration of metal ions or oxygen vacancies in the ZrO2 crystal lattice, improving resistance switching properties of Zr2-based ReRAM.

Unification of three multiphonon trap-assisted tunneling mechanisms

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Improvement of resistive switching properties in ZrO 2 - based ReRAM with implanted metal ions

On 12-in wafers of 65-nm-node floating gate NOR flash memory, charge pumping measurements show that compared to those on the edge dies (type A), the devices on the central dies (type B) have more severe damage in the source (S) and drain (D) regions. In type-B devices, the worse damage is due to the generation of interface traps in the S/channel overlapping region and the generation of bulk traps in the S and D junction region. In type-A devices, the damage is much weaker. The generation of interface traps is observed in the S/channel overlapping region. However, it is hardly measurable on the D side. The endurance characteristics have been measured in these two kinds of devices under the channel hot electron program and Fowler-Nordheim erase. In type-B devices, after program/erase cycling the memory window closure is more serious and the junction leakage also degrades greatly with the generation of a lot of bulk traps at S and D regions. The damage in fresh devices is suggested to be due to the plasma etching processes.