Hyoung-Sub Kim

Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

In this work, we present the electrical and material characteristics of TaN∕HfO2∕In0.53Ga0.47As and InP substrate metal-oxide-semiconductor capacitors and self-aligned n-channel metal-oxide-semiconductor field effect transistor (n-MOSFET) with physical vapor deposition Si interface passivation layer. Excellent electrical characteristics, thin equivalent oxide thickness (∼1.7nm), and small frequency dispersion (<2%) were obtained. n-channel high-k InGaAs- and InP-MOSFETs with good transistor behavior and good split capacitance-voltage (C-V) characteristics on In0.53Ga0.47As and InP substrates have also been demonstrated.

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel oxygen-scavenging effect technique without incorporation of nitrogen or other dopants such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for undoped HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to scavenging effect that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.

Gate oxide scaling down in HfO2-GaAs metal-oxide-semiconductor capacitor using germanium interfacial passivation layer

The primary goal of this work is to investigate the capability of gate oxide scaling down in HfO2-based GaAs metal-oxide-semiconductor capacitor (MOSCAP) using a thin germanium (Ge) interfacial passivation layer (IPL). With HfO2 of 45–50A, an equivalent oxide thickness (EOT) of 8.7A was achieved with a low gate oxide leakage current density (Jg) of (2–4)×10−3A∕cm2 at VG−VFB=1.0V. This is the thinnest EOT thickness ever reported for high-k III-V MOSCAPs. On the other hand, with thicker HfO2 of 100–110A, an EOT of 20–22A with Jg of (2–4)×10−6A∕cm2 at VG−VFB=1.0V was attained. In addition, breakdown voltages of gate oxide and hysteresis characteristics according to different thicknesses of HfO2 were studied. The results indicate that a Ge IPL and thin HfO2 enable excellent gate oxide scaling down in GaAs system.

Gate-first inversion-type InP metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Al2O3 gate dielectric

We present n-channel enhancement-mode inversion-type indium phosphide (InP) metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Al2O3 gate dielectric. It has been found that applying sulfur passivation and postdeposition annealing in the process improves the drive current and subthreshold swing. Transistors on semi-insulating InP substrates show much higher drive current than the ones on p-type InP due to the asymmetric distribution of interface state along the bandgap between InP and Al2O3. The effects of transient and slow traps on the transistor performance have also been investigated using constant electrical stress measurements and pulse measurements.

Inversion-type indium phosphide metal-oxide-semiconductor field-effect transistors with equivalent oxide thickness of 12Å using stacked HfAlOx∕HfO2 gate dielectric

We present InP metal-oxide-semiconductor capacitors (MOSCAPs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) with stacked HfAlOx∕HfO2 gate dielectric deposited by atomic layer deposition. Compared with single HfO2, the use of stacked HfAlOx∕HfO2 results in better interface quality with InP substrate, as illustrated by smaller frequency dispersion and lower leakage current density. The equivalent oxide thickness of MOSCAPs with 10A HfAlOx∕25A HfO2 stacked gate dielectric is 12A. The MOSFETs with this gate dielectric achieve two times higher transconductance than those with single 35A HfO2. They also exhibit drive current of 60mA∕mm and subthreshold swing of 83mV/decade for 5μm gate length.

Hafnium Titanate bilayer structure multimetal dielectric nMOSCAPs

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bilayer multimetal oxide dielectric has been developed for high-performance CMOS applications. Ultrathin equivalent oxide thickness (/spl sim/8 /spl Aring/) has been achieved with increased effective permittivity (k/spl sim/36). Hysteresis was significantly reduced using the bilayer dielectric. Top TiO/sub 2/ layer was found to induce effective negative charge from the flatband voltage shift. Leakage current characteristic was slightly higher than control HfO/sub 2/, and this is believed to be due to the lower band offset of TiO/sub 2/. However, the interface state density of this bilayer structure was found to be similar to that of HfO/sub 2/ MOSCAP because the bottom layer is HfO/sub 2/. These results demonstrate the feasibility of new multimetal dielectric application for future CMOS technology.

Characteristics of sputtered Hf1−xSixO2∕Si∕GaAs gate stacks

Sputtered Hf1−xSixO2∕Si∕n-type GaAs gate stacks with x=0, 30%, and 47% have been characterized using x-ray photoelectron spectroscopy, photoluminescence, and capacitance-voltage (CV) measurements. Incorporating Si into HfO2 improves both frequency dispersion and hysteresis. Compared to HfO2, 30% and 47% Hf1−xSixO2 have a lower interface state density and stronger photoluminescence intensity. At the same capacitance equivalent thickness, HfO2 and 30% Hf1−xSixO2 have a smaller leakage current density than 47% Hf1−xSixO2. It is concluded that Hf1−xSixO2 with the composition near 30% is a good high-k dielectric candidate for metal-oxide-semiconductor device application.

Improved electrical and material characteristics of HfTaO gate dielectrics with high crystallization temperature

N-type metal-oxide-semiconductor field-effect transistors (N-MOSFETs) using HfTaO with varying Ta composition (20%, 30%, 40%, and 50%) have been fabricated and characterized. Crystallization temperatures of HfTaO with varying Ta composition were also measured. It was found that HfTaO with 40% Ta exhibited the highest crystallization temperature of 900u2009°C, while 35% and 52% HfTaO showed crystallization temperature of 800u2009°C. The results demonstrate that HfTaO N-MOSFETs exhibit higher electron mobility than controlled HfO2 devices. Among them, the transistor with 40% Ta shows the highest electron mobility.

Strain additivity in III-V channels for CMOSFETs beyond 22nm technology node

For the first time strain additivity on III-V using prototypical (100) GaAs n- and p-MOSFETs is studied via wafer bending experiments and piezoresistance coefficients are extracted and compared with those for Si and Ge MOSFETs. Further understanding of these results is obtained by using multi-valley conduction band model for n-MOS and performing k.p simulations for p-MOS. For GaAs n-MOSFET, uniaxial tensile stress is shown to enhance performance only for small stresses biaxial tensile stress is shown to be more beneficial. Importantly uniaxial compressive stress is beneficial for GaAs pMOSFETs and the piezoresistance effect is much larger than that seen for Si MOSFETs along the <110> channel direction. This works shows that intrinsic mobility and stress induced mobility enhancement are key knobs for scaling of III-V CMOSFETs.

Temperature effects of Si interface passivation layer deposition on high-k III-V metal-oxide-semiconductor characteristics

In this work, we studied the electrical characteristics of TaN∕HfO2∕GaAs metal-oxide-semiconductor capacitors with Si interface passivation layer (IPL) under various postdeposition anneal (PDA) conditions and various Si deposition temperatures/times. Using optimal Si IPL under reasonable PDA, post metal anneal conditions, and various Si deposition temperatures, excellent electrical characteristics with low frequency dispersion (<5%, and 50mV) and reasonable Dit value (∼1012eV−1cm−2) can be obtained. It was found that higher temperature of Si IPL deposition and longer PDA time at 600°C improved equivalent oxide thickness and leakage current.